Hi all!
I have this circuit in a book that i read but i don't understand why its gain is 4412.
Can anyone help me to explain that??
I'm really bad to analyse because i'm a begginer!!
Thank you very much

 

Well, the simple answer is given in the drawing. An input signal of 0.68mV AC is amplified to a 3V output. That voltage ratio is 4,412.

 

There is nothing about that circuit that assures the gain is 4412. It could be anywhere from ~3000 to ~5000.

 

Gain=Output/Input=3/0.00068=4411.7

 

The problem is that the gain depends on the quality of the transistors. There are no resistor networks in that circuit that force a certain gain. A good designer would fear to put this into production because it is not repeatable in the dozens or hundreds of finished products unless you hand pick the transistors.

 

The transconductance of a BJT is fairly repeatable from unit to unit (gm = Ic/Vt where Vt ~ 26mV @ 25C) so the gain could be determined from that. But since the transconductance is related to the collector current, I don't see how that can be determined without knowing the supply voltages to determine the circuit bias currents (which are not given).

 

I reckon one could make some reasonable assumptions about the bias conditions on the basis of the schematic - albeit in the absence of the actual supply rail voltages.
For Q3 to be properly biased one would expect a current of about 2mA in Q1. If Q1 & Q2 are "matched" & have equal quiescent bias currents then the current in R3 would be around 4mA. For equal biasing of Q1 & Q2 the Q3 collector voltage would be close to 0V.
Suppose all transistors have a DC current gain of 250 then the base currents for Q1 & Q2 would be ~8uA. This would mean a DC drop across R1 & R4 of 8V. So adding up the voltage drops to give the V+ rail would result in 8+VBE+4*3.9= ~24V.
It's interesting to speculate on the most critical component values. Q1 & Q2 HFE values come into play in this regard, if the Q1 & Q2 collector currents are to be fixed at ~2mA. Clearly, the subsequent choice of R1 & R4 has a significant impact on the required value of V+.
Reducing the value of R1 & R4 from 1 Meg to say 100k will change things radically, in particular the required V+ . In turn, the value of V+ has a big influence on Q3 current if the Q3 collector voltage is constrained to be close to 0V, either by a judicious selection of R2 or perhaps by a trim pot instead of (or including a lower) R2. Q3 stage gain is highly dependent on Q3 collector current.
The 27mV signal level shown at Q3 (with 0.68mV input) seems rather inconsistent. The differential pair load resistance R2 will be loaded by Q3 input resistance. Even with R2 ideally unloaded, the Q1 & Q2 collector currents would need to be ~6mA to give the apparent gain of ~40 for the differential stage. I would think the differential stage gain would more likely be less than 10.

 

Why all the speculation? The input and output are both given in the drawing, and therefore the gain is also given. Done. The circuit could be a black box, same result.

 

The original question wasn't what is the gain, but why. Why is because there are two transistors in series, both running wide open. That is, there is no no negative feedback or degeneration to stabilize the gain of either stage. In very round numbers, if each transistor has a gain of 200 (a reasonable value for the right collector current), the series gain is 200x200=4000. ish. As mentioned above, that number will vary with system voltage and air temperature, and also will vary from one transistor to the next.

ak

 

no negative feedback? how about the output going to the base of the second transistor and controling the emitter bias of the first transistor?

 

no negative feedback? how about the output going to the base of the second transistor and controling the emitter bias of the first transistor?

That is only for DC operating bias; it does nothing to determine the AC gain, which is claimed to be 4417. Notice the 470uF capacitor in that path...

 

thats to slow down the feedback. the rc time constant of the 1 meg and the cap slow down the action of the feedback. if you didnt do this, te amp woul clamp itsself too hard and distort.
you have to remember that the ac componant of the output is impressed on the dc supply for the output transistor, so the cap charges up to the average dc value of the output. look up integrator circuit.

 

The original question wasn't what is the gain, but why.

And I say the answer is, because it says so, by defining the input and output voltages.

But maybe you're right, maybe the OP was looking for an in-depth understanding of how it works.

We may never know the OP's original intent, as he seems to be long gone from this thread.

 

Here is a simulation. I didn't know what the original supply voltages were, so I used +-15V. I didn't have the exact PNP model, but I used one that is similar, but with a higher Hfe. I had to adjust the bias by varying R5 to get V(out) more or less centered.

First, look at the time domain analysis with a 0.68mVpp 1Khz (mid band) input. Green trace is with R5=300; White trace is with R5=800; steps of 100 in between. Highest gain, but with output offset low occurs with R5=800.



Now look at the freq domain analysis with a 1mV input between 10 Hz and 1 MHz. Peak mid-band gain at 3kHz with R5=800 is about 5700 (75db).



This amplifier has no AC feedback; only DC feedback to establish its DC operating point. That is why it is so sensitive to resistor values, etc.