Q. Design an absolute address decoding scheme for an 8088 based system with 512 kbytes of Static RAM and 128 kbytes of ROM reserved for BIOS. All RAM chips available are of size 128k X 8 and the ROM chips are of size 64k X 4. The BIOS is residing at the top of the one mega byte memory limit.
The BIOS is programmed in the ROM while the RAM starts at address 40000h. You may use two separate decoder chips to generate chip select for the ROM and the RAM.
a. Memory Space map
b. Proper address decoding scheme.
c. Schematic Diagram
Ans. I am using 4 128kx8 RAM chips to synthesize the RAM while the ROM is made up of 4 64kx4 ROM chips. I decided to use the same chip select for two 64kx4 ROM chips so that they can function as one 64kx8 ROM chip together. I did this because the 8088 data bus is 8 bits wide.
I have used two decoders; a 3x8 one for the RAM and a 4x16 one for the ROM. This is necessary because the lines reserved for address generation for the RAM and the ROM are different owing to the different geometry of the chips that have been used to synthesize them; two 64kx8 ROM chips and four 128kx8 RAM hips. I have only connected the decoder outputs that respond to the desired chip select code for the RAM and the ROM respectively. For example, the 3x8 decoder has only been interfaced with the RAM for outputs O2, O3, O4 and O5 because they are produced in response to the RAM chip select code. Since all the other connections have been left floating, only the aforementioned outputs are valid outputs and will serve as chip select for the RAM. I know this isn't exactly economical and I could have easily used a bunch of NAND gates or something to achieve the same thing but what I am mainly interested is whether I am right or wrong. So what do you guys think?
Overview of the Schematic:
. Lines A17-A19 are fed into a 3x8 decoder and its output is used to select one of the 4 RAM chips used to synthesize the RAM.
. The rest of the lines i.e. lines A0-A16 are fed into each RAM chip for the purpose of address generation or accessing a memory location within the memory.
. In addition, lines D0-D7 are also being fed into each RAM chip to READ or WRITE data.
Here is the memory space map: https://imageshack.us/a/img600/5971/memoryspacemap.jpg
Here is the entire schematic: https://imageshack.us/a/img202/3055/schematicq1.jpg
P.S. There is a bunch of stuff missing in the schematic up there. I haven't hooked up the data bus to the RAM and I have also skipped the READ and WRITE signals. And I haven't shown the address decoding process for the ROMS either.
I am an undergrad student. I really appreciate the help. Thanks in advance.
The BIOS is programmed in the ROM while the RAM starts at address 40000h. You may use two separate decoder chips to generate chip select for the ROM and the RAM.
a. Memory Space map
b. Proper address decoding scheme.
c. Schematic Diagram
Ans. I am using 4 128kx8 RAM chips to synthesize the RAM while the ROM is made up of 4 64kx4 ROM chips. I decided to use the same chip select for two 64kx4 ROM chips so that they can function as one 64kx8 ROM chip together. I did this because the 8088 data bus is 8 bits wide.
I have used two decoders; a 3x8 one for the RAM and a 4x16 one for the ROM. This is necessary because the lines reserved for address generation for the RAM and the ROM are different owing to the different geometry of the chips that have been used to synthesize them; two 64kx8 ROM chips and four 128kx8 RAM hips. I have only connected the decoder outputs that respond to the desired chip select code for the RAM and the ROM respectively. For example, the 3x8 decoder has only been interfaced with the RAM for outputs O2, O3, O4 and O5 because they are produced in response to the RAM chip select code. Since all the other connections have been left floating, only the aforementioned outputs are valid outputs and will serve as chip select for the RAM. I know this isn't exactly economical and I could have easily used a bunch of NAND gates or something to achieve the same thing but what I am mainly interested is whether I am right or wrong. So what do you guys think?
Overview of the Schematic:
. Lines A17-A19 are fed into a 3x8 decoder and its output is used to select one of the 4 RAM chips used to synthesize the RAM.
. The rest of the lines i.e. lines A0-A16 are fed into each RAM chip for the purpose of address generation or accessing a memory location within the memory.
. In addition, lines D0-D7 are also being fed into each RAM chip to READ or WRITE data.
Here is the memory space map: https://imageshack.us/a/img600/5971/memoryspacemap.jpg
Here is the entire schematic: https://imageshack.us/a/img202/3055/schematicq1.jpg
P.S. There is a bunch of stuff missing in the schematic up there. I haven't hooked up the data bus to the RAM and I have also skipped the READ and WRITE signals. And I haven't shown the address decoding process for the ROMS either.
I am an undergrad student. I really appreciate the help. Thanks in advance.
