hi 680,
The point I am making is that the test pattern of A, B CYi , of the LTS is set to prove the OR function.

In order to check the full adder operation you need to modify the A,B CYin test voltages , so that you get all the possible input states.

Do you follow what I am saying.
E

yes i got it that to implement all the states and show the functioning of full adder i need to change the test voltages of a b and cin but how do i go about doing that? i dont have any clue regarding it. So far i have only worked with .DC mostly. Can u please help me with that?

 

hi,
Check this quick version of the test pattern

If OK, connect to the Adder inputs and check its performance.

E

 

hi,
Check this quick version of the test pattern

If OK, connect to the Adder inputs and check its performance.

E

yes these look good i will update the output results immediately

 

hi,
I would say the Sum and CYO are incorrect,.
The Test inputs A,B, CYI are as the Adder table, but the outputs are wrong.

Check your diode are wiring network.

Do you know if the Adder as posted on that link was correct and fully tested.???


E

Update:
Check the output line of the CYI inverter, there is something loading the signal on that line.

 

hi,
Check this quick version of the test pattern

If OK, connect to the Adder inputs and check its performance.

E

hey so i got this i feel something is wrong

 

hi,
I would say the Sum and CYO are incorrect,.
The Test inputs A,B, CYI are as the Adder table, but the outputs are wrong.

Check your diode are wiring network.

Do you know if the Adder as posted on that link was correct and fully tested.???


E

Update:
Check the output line of the CYI inverter, there is something loading the signal on that line.

i think mostly the circuit posted on that site is correct and should give the correct output as it also looks like a LTspice diagram

 

i think mostly the circuit posted on that site is correct and should give the correct output as it also looks like a LTspice diagram

yes the loading on the inverter cyi seems missing but i have given it the mentioned value look

 

hi,
No, as I say there is problem with the diode matrix.
I have marked the image with dark Blue lines showing what SUM and CYout should be.
Check against the table.


E

 

yes i

hi,
No, as I say there is problem with the diode matrix.
I have marked the image with dark Blue lines showing what SUM and CYout should be.
Check against the table.


E

yes I already realised this. Its not matching the desired output table i think all connections are correct according to that diagram. what are your thoughts about this?

If at all anything is not possible can you send me the input draft only till the part the output is correct?

 

hi,
I suspect the original design was never fully tested.

I am not sure what you mean.?
send me the input draft only till the part the output is correct?

E

 

hi,
I suspect the original design was never fully tested.

I am not sure what you mean.?
send me the input draft only till the part the output is correct?

E

hi,
I suspect the original design was never fully tested.

I am not sure what you mean.?
send me the input draft only till the part the output is correct?

E

yeah actually i thought executing it only for the parts it is showing correct output but what do u suggest me doing now?

 

hi,
Would suggest that you submit to your tutor, the 'marked up' corrected plots and simulations with an explanation of why you think the original circuit you discovered is at fault.

E

 

hi,
Would suggest that you submit to your tutor, the 'marked up' corrected plots and simulations with an explanation of why you think the original circuit you discovered is at fault.

E

Yeah I think of doing the same. According to you, what is wrong in the orignal circuit?

 

I have attached below the asc file of my circuit, the truth table, the desired output with a marker trace and my obtained output.

refernce used: https://hackaday.io/project/11860-diodes-only/log/52981-diode-full-adder

Please help me how do I achieve the desired output?

 

hi 680.
Hard wired the A,B,CYI Low and the /A,/B /CYI High and it still outputs Sum and CYO as high.

Ask the Author of the circuit for confirmation that it works.

E

 

hi 680.
Hard wired the A,B,CYI Low and the /A,/B /CYI High and it still outputs Sum and CYO as high.

Ask the Author of the circuit for confirmation that it works.

E

i contacted the author he asked me that the pull-ups and pull-downs should not be the same value , the thresholds for the output buffers need to be adjusted , the resistor values 47k for all resistors using 5V inputs are probably incorrect and also the inverters should not be present for the true outputs. What are your suggestions on these?

 

hi 680,
The fact he does not know the resistor values, are probably incorrect , suggests to me that he never had the circuit working.
What did he suggest for the Threshold levels.?
Post a circuit with his 'suggestions' and I will simulate, see what we get.
E

 

hi 680,
On this image from LTS, I have Set A,B , CYI low and /A,/B, /CYI high,, the SUM and CYO should be Low [as per the Adder Table], they are High.!

E

 

hi 680,
Tried to make sense of the comments from the author, this is looking better.
Why did he say 6 Inverters.??
E

Update:
Added the image I used for tracing the non invert.

 

hi 680.
Hard wired the A,B,CYI Low and the /A,/B /CYI High and it still outputs Sum and CYO as high.

Ask the Author of the circuit for confirmation that it works.

E

Voila! So after all the changes the circuit is now correct and functional. Can you please guide me as to how is this circuit working and the circuit analysis ?