# From boolean algebra to logic gates

#### project_science

Joined Sep 14, 2018
21
Hi,

I developed a Boolean algebraic expression from a truth table. I'm now trying to implementing the expression into logic gates. First time I've done this, and I want to make sure I'm on the right track. Please see my attached work and let me know if I made some error(s) or if it makes sense.

Note that I put the expression in the logic gate for clarity of what the gate is supposed to be doing, but I'm not sure if that's conventional.

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#### Xavier Pacheco Paulino

Joined Oct 21, 2015
728
The 4-input AND gate F(A,B,C) should be an OR gate.

#### WBahn

Joined Mar 31, 2012
26,398
Your first term is hard to tell if it is (ABC)' or (AB)'C. Need to be very careful when writing this stuff out.

As already noted, your final gate needs to be an OR gate, not an AND gate.

#### dl324

Joined Mar 30, 2015
12,263
The circuit in question:

#### project_science

Joined Sep 14, 2018
21
1. Yes WBahn, I can do better. It should be (ABC)' on the first term. In fact, that's more clear than a hat on top.
2. I corrected the final AND gate to be an OR. That makes sense as if ANY of the 3-input combination gates are true, then the output is true.

#### project_science

Joined Sep 14, 2018
21
Hi,

Below I’m trying to implement F(A,B,C) using only 2-input NAND gates. I think my first step it to simplify the original 3-term F(A,B,C) or Boolean terms into 2-term Boolean product terms.

Attached is my work. I’ve labeled the Boolean laws I’ve used before each reduction, omitting obvious steps. (I’ve used this URL as my source for Boolean Laws: https://www.electronics-tutorials.ws/boolean/bool_6.html)

Below that, I’ve attempted to show the gates.

Admittedly, I don’t think I’m correct for the following reasons:

1. The expression (ABC)’ + ABC = 1 seems to be problematic, as this 1 will then gobble up all the other terms by the Annulment Law.
2. The HW asks for 2-terms inputs using only NAND gates, and I’m using a NOT gate for a single input before using the NAND gate.

3. Implementing a “1” into a logic gate doesn’t seem to make sense to me.

Since there’s a few problems here, I think the first step is to tackle the F(A,B,C) reduction, but what I’ve shown is as far as I’ve gotten. Any tips?

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#### MrChips

Joined Oct 2, 2009
22,555
Are you sure that what you have written is the correct question?

What is outcome of the following?

F = A + 1

#### WBahn

Joined Mar 31, 2012
26,398
1. Yes WBahn, I can do better. It should be (ABC)' on the first term. In fact, that's more clear than a hat on top.
2. I corrected the final AND gate to be an OR. That makes sense as if ANY of the 3-input combination gates are true, then the output is true.
Sounds good. One very good habit to get into is reviewing your work as you go -- in essence, you do the problem twice, but the second time the focus is on confirming that what you just did is correct and makes sense. We all make silly mistakes all the time, so getting into this habit will be a HUGE time saver down the road.

#### WBahn

Joined Mar 31, 2012
26,398
Hi,

Below I’m trying to implement F(A,B,C) using only 2-input NAND gates. I think my first step it to simplify the original 3-term F(A,B,C) or Boolean terms into 2-term Boolean product terms.

Attached is my work. I’ve labeled the Boolean laws I’ve used before each reduction, omitting obvious steps. (I’ve used this URL as my source for Boolean Laws: https://www.electronics-tutorials.ws/boolean/bool_6.html)

Below that, I’ve attempted to show the gates.

Admittedly, I don’t think I’m correct for the following reasons:

1. The expression (ABC)’ + ABC = 1 seems to be problematic, as this 1 will then gobble up all the other terms by the Annulment Law.
Your thinking is correct, so kudos for asking if the result makes sense (something that a lot of people don't do). While this is a big red warming flag, it IS possible that the original problem works out to be always 1, so look at the original problem and see if you can figure out a combination of the three inputs that will make the output 0 -- for instance, if A is false that kills the last three terms, so now you just need to kill the first term. But if A is false, then that forces the first term to be true regardless of B or C. So let's turn that around. The only way to kill the first term is for A, B, and C to all be true, but if they are, then we can't kill the last term.

2. The HW asks for 2-terms inputs using only NAND gates, and I’m using a NOT gate for a single input before using the NAND gate.
So think about how you might make a NOT gate if all you had was a NAND gate.

3. Implementing a “1” into a logic gate doesn’t seem to make sense to me.
If that's what you need, it's not a problem.

Since there’s a few problems here, I think the first step is to tackle the F(A,B,C) reduction, but what I’ve shown is as far as I’ve gotten. Any tips?
Consider the feedback above. If necessary, draw a truth table for the function.

Remember, there is a difference between (ABC)' and (A')(B')(C'). So you might look carefully at the original problem and see if it is a single overbar over the entire term, or separate overbars over each variable. The same with your second term -- verify that it really is A(BC)' and not (A)(B')(C').