Hi

I start playing with this fpga tang nano, there are really few information around and I am struggling with configuration.
I found some example for led which I understood how to import and compile the project. I am learing verilog so I also
familiar with modules. Problem is physical constrain file:

I am looking here, the pinout:
https://tangnano.sipeed.com/en/

When you define something like that :
IO_LOC "led[0]" 16;

You are naming the inputs/outputs variables you will use in your module,
you are telling the Synthesize tool to write to pin 16 when you use the led reg as output.
Now I see from the pinout that each pin has different purpose, so for example I can use pin 16 also as input? How I can define
in the constrain that I want for example pin 16 to be an input from external (i.e. external button I add to the board)?
How I can define for example that pins from 27 to 34 are external inputs ?
What is the meaning of bank? Is there any selector for the bank ?

Thank you.

 

There are several simple tutorials on the IDE installation page. They will show the information you need on assigning pins:
https://tangnano.sipeed.com/en/get_started/install-the-ide.html

 

Yep, thank you, but I don't get from these example answers to my doubts. I don't understand if pin 16 it can only be used to drive the led or it can be used also as input from external resource , if so how to define constrains. Very poor info online.

 

no help ?

 

Yep, thank you, but I don't get from these example answers to my doubts. I don't understand if pin 16 it can only be used to drive the led or it can be used also as input from external resource , if so how to define constrains. Very poor info online.

Hello @supertony,

currently i have permanent lack of time (job tasks) so my answer will be very short (sorry I didn,t noticed your last post).
Information about pin is input or output one has defining in VHDL code of module/entity. For example (Verilog):

module breakout(

    input clk50,
    input rota,
    input rotb,
     input de,
    output  red,
    output  green,
    output blue,
    output hsync,
    output vsync
    );

In constraint file, one is giving basically electrical information or buffer function of the pins - see example:

/Copyright (C)2014-2020 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//GOWIN Version: V1.9.3.01Beta
//Part Number: GW1N-LV1QN48C6/I5
//Created Time: Thu 10 01 15:28:00 2020

IO_LOC "clk24" 35;
IO_PORT "clk24" IO_TYPE=LVCMOS33 PULL_MODE=NONE;

IO_LOC "rota" 14;
IO_PORT "rota" IO_TYPE=LVCMOS33;

IO_LOC "rotb" 15;
IO_PORT "rotb" IO_TYPE=LVCMOS33;

IO_LOC "de" 20;
IO_PORT "de" IO_TYPE=LVCMOS33;

IO_LOC "red" 24;
IO_PORT "red" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=12;

IO_LOC "green" 21;
IO_PORT "green" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=12;

IO_LOC "blue" 19;
IO_PORT "blue" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=12;

IO_LOC "hsync" 22;
IO_PORT "hsync" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=12;

IO_LOC "vsync" 23;
IO_PORT "vsync" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=12;

There is also IDE graphical function in which you can define the definition of every pin and you have many support and hints about its functions. See also this link - I found many information about defining pins for Tang Nano FPGA in this post:

https://www.bananatronics.org/first-steps-with-the-tang-nano-fpga-development-board/

You can also try to translate my thread on Polish forum about electronics - where I described implementation of simple version of "Breakout" game on "Tang Nano":
https://forbot.pl/forum/topic/18642...e-fpga-elbert-v2/?tab=comments#comment-168785

Here is translation to English (by Google Translate - link:
https://forbot-pl.translate.goog/fo...l=en&_x_tr_hl=pl&_x_tr_pto=nui#comment-168785


Best Regards

 

Hi thank you. I did some test on the board like connecting some external logical analyzer and i see that the same data is sent also to those external pins, so when led is blinking data is send also to pin 16 . Thanks again for info I will give a look

 

Hi @FlyingDutch how are you? I am generating a clock pulse with fpga tang nano .... it may seems a silly question but what would be the H voltage level I should expect from the output ? Shouldn't be around 5V ? I measured with an osc and seems very low.... I want to provide this clock to a microcontroller.

 

Hi @FlyingDutch how are you? I am generating a clock pulse with fpga tang nano .... it may seems a silly question but what would be the H voltage level I should expect from the output ? Shouldn't be around 5V ? I measured with an osc and seems very low.... I want to provide this clock to a microcontroller.

Hello @supertony,

if you defined it like this:

IO_LOC "clk24" 35;
IO_PORT "clk24" IO_TYPE=LVCMOS33 PULL_MODE=NONE;

the amplitude should be 3.3V, but if you use:

IO_LOC "clk24" 35;
IO_PORT "clk24" IO_TYPE=LVCMOS18 PULL_MODE=NONE;

the amplitude should be 1.8 V

Because the clock has high frequency it also depends of used scope (the amplitude shown by scope can be a bit lower than standard). How voltage is logic level of this MCU - is it 3.3V or 5V or less than 3.3V? You can use a "shift level converter" - for example one of these:
https://www.mouser.pl/ProductDetail/Texas-Instruments/SN74LV1T34DBVRG4?qs=vdi0iO8H4N10R%2Bt%2BjmxZrg==&mgh=1&vip=1&gclid=Cj0KCQiAi9mPBhCJARIsAHchl1xn9HM7Yy1Y_5wqOAuWFgeTYrelXP9GT7YeGHX9XewzZJ8j2dCXGo8aAqjwEALw_wcB

https://botland.store/voltage-conve...ional-converter-4-channel--5903351248709.html

Of course you have to change in expression: IO_LOC "clk24" 35; -> the "clk24" with name of clock signal used in your project.

BTW: if ypu want to connect FPGA clock to MCU it is better to use a CMOS gate as a buffer for it.

Best Regards

 

May be one thing of use,

In a FPGA , there are two "file types" of relevance here,
The code files,
they define what the circuit does,
they define "ports" by name, that can be input , output or bi directional

Then there is separately a pin configuration file,
This as a minimum specifies which port of the code, connects to which real pin on the chip,
also can specify the pins voltage, drive strength , type ( cmos, VDS ) etc.

There is a third file type, that can in some tools be combined in the same file as the pin specifications
that specifies the timing constraints, based upon the port names of code

The advantage of this system,
is that FPGA code, i.e. HDL, is transportable,
to use the same code on a different chip, only the pin configuration needs to be changed,