# Flip Flop Triggering on Rising Edge, Not falling edge as it should

Discussion in 'General Electronics Chat' started by imzack, Feb 5, 2015.

1. ### imzack Thread Starter Well-Known Member

Nov 3, 2010
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I have a flip flop at I have set up so it only cares about falling edges. I have a couple units however that when they get a little bit warmer, they start to trigger on the rising edge of the clock line. Any ideas on what is going on? I have looked at the scope trace, and zoomed in, the clock signal is going from 0 to 5 volts, with little time inbetween (aka 2v, to 3v, to 4v). Somewhere at around 3 volts though, the JK Flip Flop triggers on the rising edge instead of the falling edge as it should be. Why does the flip flop think the rising edge is a falling edge? Also, why does it behave this way when its warm, but if I try to cool the unit down a few degrees the unit acts as excepted?

Thanks

Jan 15, 2015
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A drawing would be nice? Can you post a drawing of the circuit?

Ron

3. ### WBahn Moderator

Mar 31, 2012
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A drawing would be awfully nice.

Where does the clock signal come from?

My initial guess is that you are deriving your clock from a source that is glitching and the flip flop, when warm, is fast enough to respond to lower energy glitch signals than it can when it is cool.

4. ### MrChips Moderator

Oct 2, 2009
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Which flip-flop? Part number?

Noise on the clock signal? What is generating the clock signal? What is the rise time and fall time of the clock signal?

5. ### imzack Thread Starter Well-Known Member

Nov 3, 2010
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Sorry about the delay on this. But I believe it to be how fast the rising and falling edges are of the clock signal.

What inside the JK Flip Flop dictates how slow of a rising and falling edge time that is acceptable?

6. ### WBahn Moderator

Mar 31, 2012
24,075
7,473
It can be any number of things -- it all depends on the details of the design. If it's CMOS, the details of the transistor thresholds plays a big role because they determine the degree of shoot through current you get and also the degree to which nodes have to act as charge-storage nodes during the transition.

Nov 3, 2010
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