Can the Drain and Source for a P-channel enhancement FET be swapped??
I have a circuit that has a P-channel Enhancement mode FET with the drain connected to +5V. The Gate is either pulled to +5V via a pull-up resistor or pulled LO via another transistor. The source of the FET is connected to the output signal.
The transistor works fine when the gate is pulled to 0V (connects the source to +5V drain.) However, when the gate is pulled to +5V, the FET holds the source at +4.72V instead of being disconnected. I am wondering whether the source and drain are simply swapped by mistake?? Any help....
Thanks!!
I have a circuit that has a P-channel Enhancement mode FET with the drain connected to +5V. The Gate is either pulled to +5V via a pull-up resistor or pulled LO via another transistor. The source of the FET is connected to the output signal.
The transistor works fine when the gate is pulled to 0V (connects the source to +5V drain.) However, when the gate is pulled to +5V, the FET holds the source at +4.72V instead of being disconnected. I am wondering whether the source and drain are simply swapped by mistake?? Any help....
Thanks!!