FET switch (PWM) I have done something wrong... Can you help

Discussion in 'General Electronics Chat' started by Dyslexicbloke, Apr 30, 2016.

  1. Dyslexicbloke

    Thread Starter Well-Known Member

    Sep 4, 2010
    I have previously posted this circuit, asking about RFI, but I have a fundamental problem somewhere.
    The resistor in parallel with the zenner is actually 6k8

    Testing this with a PSU on the left, and a load on the right seems to work.
    Configured as drawn its ok until the power go's up when I see an unstable oscillation when the FET is supposed to be off.

    I am reasonably sure the cause could be identified If I could measure it but as the FET's immediately get very hot leaving insufficient time to investigate.
    I suspect that the slew rate of the transistor base node is too slow and as the FET turns off the PV voltage climes faster than the base node thus increasing VGS and turning the FET back on again. I am assuming VPV is recovering slowly in partial sun and quickly in full sun.

    Does my scenario sound plausible? I am asking because testing it will be hard.

    Given that I am aiming for VGS <1v and VGS > VPV-12V is there a batter way to shift the 5V control signal?

    I have dropped the PWM frequency to 40Hz for testing and the oscillation is evident for the whole of period.

    Basically I am trying to make a solid state relay circuit that can operate with a PWM frequency above 20kHz
    I would appreciate comments, good or bad, and should be able to perform any suggested tests in the morning but only if there is enough sun.

    I did remove the 223 caps but all that seemed to do was make the switching spikes higher.
  2. dannyf

    Well-Known Member

    Sep 13, 2015
    From the datasheet, find the gate charge of the mosfet. that number x switch frequencies gives the minimum current needed to drive one such device.

    I would double it to be comfortable. That provides the minimum drive current requirement for your driver.

    BTW, watch out for shoot-through on the driver and conduction losses on the mosfet.
  3. crutschow


    Mar 14, 2008
    Try changing the 6k8Ω resistor to about a 2k0Ω.
  4. Dyslexicbloke

    Thread Starter Well-Known Member

    Sep 4, 2010

    I presume that is nano Coulombs so would 4000Hz X 0.000000063C be correct, if so its only 252uA
    That sounds impossibly small, what did I get wrong I cant be 4000 X 63...

    RDS on is about 0.6 cold snd almost 2 hot which I cant leave them on long to test

    My problem is lack of knowledge, in that I dont appreciate the significance of much of the datasheet.
    I assume conduction losses are power dissipation when on and during transitions when the device is not fully on, ids this correct?

    What is shoot through and what should I be doing about it?
    How is this done commercially? I

    Thanks for the help
  5. crutschow


    Mar 14, 2008
    You need to look at the current required to charge and discharge the gate capacitance in a short period of time so as to minimize the switching rise/fall times and thus the dissipation
    The average current to do this is of no interest.
    Thus for a 100ns rise/fall time the required instantaneous current would be 63nc / 100ns = 630mA, obviously a fairly healthy current pulse.
    That's why I suggested reducing the value of the resistor in parallel with the zener, to reduce the rise-time of the gate signal.

    What's the current through the MOSFET when ON?
    With an ON resistance of .06Ω that MOSFET will get very hot at currents of several amps if not on a heatsink.
    You may need a MOSFET with a lower ON resistance.

    Shoot through current can be a problem in bridge circuits if two transistors in the same leg are momentarily on at the same time when the bridge is switching.
    You do not have that problem.
  6. Alec_t

    AAC Fanatic!

    Sep 17, 2013
    Try adding a pull-up resistor (a few k) from the FET gate to its source, to assist turn-off.
  7. Dyslexicbloke

    Thread Starter Well-Known Member

    Sep 4, 2010
    ' current would be 63nc / 100ns = 630mA'
    A little embarrassing I didn't know that, I know Coulombs are charge I don't think I ever used one!

    FET current could be as much as 6A, and I suspect there will be a short higher current pulse when they first turn on.
    (The PV is capable of delivering about 30A and I currently have 5 switches)

    I will modify the pull up on the base of the totem-pole as suggested, I think I can go as low as 1.8k without adversely affecting VGS when the FETs are on and the top rail is at VBat but I am wondering now if the transistors are up to the job.

    I can set up some tests If I know what I am looking for but I don't have a feel for where/why the bad interaction is taking place.
    I think I will switch off the PWM and arrange a method of manually controlling the output so I can see if the oscillation is sustained and perhaps understand its origin. If anyone has any specific suggestions with respect to what I should look for and where I would appreciate a heads up.

    There isn't much sun right now which is making testing a little tricky...

    Am I just going about this the wrong way? Perhaps a different gate drive circuit entirely?

  8. ronv

    AAC Fanatic!

    Nov 12, 2008
    Since you have a solar panel and a battery pack my guess is there is a fair amount of wire (inductance) between your circuit and both the panel and the battery. If it works at low power scope all three pins of the fet and post the pictures.
    If you can't do that add a diode from the drain to ground (cathode to the drain) .