I am trying to drive a 5ns wide pulse of variable frequency up to 100MHz into a 50 ohm load & achieve a signal level of at least 3.5V. The rise & fall times of the pulse have to be in the reion of 1ns.
The source of my signal is taken from the output of an FPGA and has a guaranteed Voh of 2.4V.
I currently have an NXP 74F3037 NAND driver connected to the output of the FPGA & I am getting a pulse of approx. 3V but the rise time is disappointing (3ns).
Does anyone have any suggestions as to how I could achieve this, either with discrete components or using a translation IC (I have looked at level translating ICs but have struggled to find one that handle the speed & pulse width).
Thanks
The source of my signal is taken from the output of an FPGA and has a guaranteed Voh of 2.4V.
I currently have an NXP 74F3037 NAND driver connected to the output of the FPGA & I am getting a pulse of approx. 3V but the rise time is disappointing (3ns).
Does anyone have any suggestions as to how I could achieve this, either with discrete components or using a translation IC (I have looked at level translating ICs but have struggled to find one that handle the speed & pulse width).
Thanks