I would like a way to estimate the delay caused by an op-amp. Is there a way to do this from the data sheet?

I am thinking the graph of phase shift versus frequency should work but I am not quite sure how. For instance what frequency would I use for the phase shift?

I would do this with LTspice but that would require a model for all of the op-amps I want to compare. The problem with this is that tracking down models for very high speed op-amps. They are hard to find even if they exist.

 

Hello,

I have here a list with highspeed opamps.

Bertus

 

Thanks @bertus. Having that list in a searchable format could be quite useful.

Only the parts near the top of the list are of interest to me. One requirement is that it must be a voltage feedback op-amp. I am looking for delays of less than 2ns. 1ns would be better.

For reference, I have looked at a few op-amps such as the ADA4817, OPA659, and LT1818. For the short term I will use the LT1818 but it is not FET input and seems a bit slow in simulation. I am leaning toward the OPA659 but it is pricey. (Yes, I am cheap).

 

I would like a way to estimate the delay caused by an op-amp. Is there a way to do this from the data sheet?

I am thinking the graph of phase shift versus frequency should work but I am not quite sure how. For instance what frequency would I use for the phase shift?

I would do this with LTspice but that would require a model for all of the op-amps I want to compare. The problem with this is that tracking down models for very high speed op-amps. They are hard to find even if they exist.

It also depends upon your gain. Greater gain means greater delay.

 

It also depends upon your gain. Greater gain means greater delay.

The gain is low. A gain of 2, non-inverting.

Why more delay at greater gains? Is this only because of reduced bandwidth?

 

You need to attach a capacitor to the output and measure the slew rate of the op op amp first. Then you measure the opamps output impedance and write it down. Then you measure the time it takes for the cap to charge up to 3 time constants. Take the time constant and divide it by the time measured in step 1. That value will be close to the delay of the opamp. OK ?

 

You need to attach a capacitor to the output and measure the slew rate of the op op amp first. Then you measure the opamps output impedance and write it down. Then you measure the time it takes for the cap to charge up to 3 time constants. Take the time constant and divide it by the time measured in step 1. That value will be close to the delay of the opamp. OK ?

I am trying to do this without Spice models or actual hardware. I am hoping there is a way to find the delay using just the data sheets for the op-amps.

 

The gain is low. A gain of 2, non-inverting.

Why more delay at greater gains? Is this only because of reduced bandwidth?

Yes, reduced bandwidth due to gain means increased delay/phase.

 

RichardO you have too much time on your hands! And you're always pushing limits - which makes me so interested in your projects.

A gain of 2 is not low when thinking in this manner. That's 6 dB up! Meaning you lose 1/2 of your gain bandwidth product! At these speeds you'll have less peaking at your closed loop gain, so this isn't all bad. The gain vs phase plot is the right place to start thinking about this I think as well. At the 6dB line you will find your frequency where you start hitting the rolloff- you will have approximately 45deg of phase shift at this frequency. But note however, that this is the open-loop gain of the amplifier - so the phase will not be accurate in the closed-loop. Some datasheets will give you the nominal gain of 2 plot also, but I don't every recall seeing the closed loop phase shift.

Some quick (i.e. off the top of my head math - so there is probably some error - please feel free to double check my math). 45 deg of phase shift at 1ns means you need a closed loop frequency of 125MHz (45deg/360deg = 1ns / period). And you need an op-amp capable of 2 times this frequency to satisfy the GBWP of a gain of 2. So you need something in the 250MHz range... I'd probably double that just to be on the safe side - 500Mhz! Good luck!

 

So, just to prove my theory, I did a quick simulation using the LT6557. 500MHz, 2200V/us slew rate, triple opamp package, factory set for a gain of 2. Convenient for our purposes! YOu may be able to put the opamps in parallel for additional drive capability and possibly improved prop delay.

The photo shows a prop delay (50% to 50%) of 1ns.

What do I win?

Based on this I'd look for an amplifier of a GBW of 500MHz that meets your other specs (power supply voltage, input/output rail-to-rail, etc). Fortunately they are somewhat prevalent these days. At these speeds it's hard to find single ended output though.

 

Also, why not consider a current feedback amplifier? Just making sure this is a real requirement. The AD8007 may fit the bill even better for you if you're willing to consider CFB amps. Much less peaking, a bit slower at a gain of +2, but will probably still meet your requirement, and is relatively cheap (~$3.50 in single piece quantity).

I recall Jim Williams once getting a requirement to use a CMOS amplifier because it was so much more 'low-power'. He was able to meet the requirements with a bipolar amplifier -- saving cost, at the time. Refer to the zoo circuit for further details.

 

So you need something in the 250MHz range... I'd probably double that just to be on the safe side - 500Mhz! Good luck!

I am looking at the OPA659. Pricey at over $7 each. Painful, but tolerable. See the attached spec.

Also, why not consider a current feedback amplifier? Just making sure this is a real requirement. The AD8007 may fit the bill even better for you if you're willing to consider CFB amps. Much less peaking, a bit slower at a gain of +2, but will probably still meet your requirement, and is relatively cheap (~$3.50 in single piece quantity).

I am using a CFB amp on the SBB prototype (LM6361). Not fast enough (100 MHz) and huge input bias current. Advantages are that I have them and they are in a DIP.
I really want a FET input to keep the input bias current small. Features of the OPA659:

• High Bandwidth: 650 MHz (G = 1 V/V)
• High Slew Rate: 2550 V/μs (4-V Step
• Excellent THD: –78 dBc at 10 MHz
• Low Input Voltage Noise: 8.9 nV/√Hz
Fast Overdrive Recovery: 8 ns
• Fast Settling time (1% 4-V Step): 8 ns
• Low Input Offset Voltage: ±1 mV
• Low Input Bias Current: ±10 pA
• High Output Current: 70 mA

On the PCB prototype I will use the LT1818 -- because it is cheap -- even though its bias current is an astronomical 8 uA.

I recall Jim Williams once getting a requirement to use a CMOS amplifier because it was so much more 'low-power'. He was able to meet the requirements with a bipolar amplifier -- saving cost, at the time. Refer to the zoo circuit for further details.

Unfortunately, I am no Jim Williams.

 

I am using a CFB amp on the SBB prototype (LM6361). Not fast enough (100 MHz) and huge input bias current.

The LM6361 isn't a CFB and it's only 50MHz... maybe you got the part number wrong?

I really want a FET input to keep the input bias current small. Features of the OPA659:

...

On the PCB prototype I will use the LT1818 -- because it is cheap -- even though its bias current is an astronomical 8 uA.

I guess what I'm try to say is, does the input bias current really load down your circuit significantly? The current feedback amplifier I'm suggesting using has a max positive input bias current of 8uA as well, but there is no peaking in the closed loop. These are pretty high bias currents by today's standards, but if it's not really a requirement, don't make it one. Usually when doing high speed, you expect to use more power, therefore higher currents flow just about everywhere.

Unfortunately, I am no Jim Williams.

None of us are!

 

The LM6361 isn't a CFB and it's only 50MHz... maybe you got the part number wrong?

Yes, I should have typed LM6181. This is one case where the LMxx1, LMxx2 and LMxx3 for different versions of the same part does not work. I attached the correct spec. sheet for you.

I guess what I'm try to say is, does the input bias current really load down your circuit significantly? The current feedback amplifier I'm suggesting using has a max positive input bias current of 8uA as well, but there is no peaking in the closed loop. These are pretty high bias currents by today's standards, but if it's not really a requirement, don't make it one. Usually when doing high speed, you expect to use more power, therefore higher currents flow just about everywhere.

The input current of the op-amp is part of the current charging and discharging the timing cap. At low frequencies on the dial, the timing current is small -- a few microamps. The effect is that the triangle time symmetry degrades as the frequency is decreased. This is because the bias current always adds to the timing current.

I am most likely going to have to live with some peaking because of capacitive loading on the output of the voltage feedback op-amp that I will actually use. Scot A. has convinced me that I need to use the OPA653. This is basically the OPA659 with two feedback resistors internal to give a gain of +2 or -1. The internal resistors get rid of the nastiness of capacitance at the summing node. See attached spec.

 

The input current of the op-amp is part of the current charging and discharging the timing cap. At low frequencies on the dial, the timing current is small -- a few microamps. The effect is that the triangle time symmetry degrades as the frequency is decreased. This is because the bias current always adds to the timing current.

Now I understand the requirement. I looked at your circuit and thought you were driving you charge caps with a constant current... it was late at night and I didn't want to do a bunch of analysis. But at low charge current this makes sense.

I am most likely going to have to live with some peaking because of capacitive loading on the output of the voltage feedback op-amp that I will actually use. Scot A. has convinced me that I need to use the OPA653. This is basically the OPA659 with two feedback resistors internal to give a gain of +2 or -1. The internal resistors get rid of the nastiness of capacitance at the summing node. See attached spec.

The peaking is not caused entirely by capacitance at the summing point. It's due to the marginal stability (lack of sufficient phase margin) of the amplifier when running at such a high rate of speed. This lack of phase margin causes peaking in the closed loop, and then ringing in the output waveform. This is due to both capacitive loading and the summing point capacitance - so it's a bit of chicken and the egg. But it's a good reminder to try to limit output capacitance as well as input capacitance. A carefully selected feedback cap (1-10pF) can also improve the phase shift and limit peaking without reducing bandwidth.

Current feedback amps work very differently, as you know, and I believe that they have less peaking due to the low input impedance at the summing node. But I could be wrong about that and would welcome better information if anyone is listening that knows more about the subject.

Have you considered a discrete buffer prior to the opamp? This app note references a "High Impedance Low Capacitance Wideband Buffer" on page 8 of the document. It doesn't really describe the bandwidth and other considerations, but it may be something to think about if you can get the best of both worlds.

 

Have you considered a discrete buffer prior to the opamp? This app note references a "High Impedance Low Capacitance Wideband Buffer" on page 8 of the document. It doesn't really describe the bandwidth and other considerations, but it may be something to think about if you can get the best of both worlds.

The problem is that I need a gain of 2. My circuit would have to be somewhat like a push-pull version of the buffer in the app. note.

I have given thought to making a version of the LH0033 buffer. I have tried to duplicate the LH0033 in the past without much success. I had somewhat better results with just the Dual J-FET front end. In fact I have that circuit on the input of my frequency counter. The biggest impediment is matching the two J-FET's.

For now, I am planning on using the OPA653. I will have to fake it in the prototypes -- accepting the limitations of whatever buffer amp I have.

p.s. The LH0033, LH0063 buffers and the LH0032 op-amp were quite amazing when I first used them in the early 1970's. I once had an LH0032 oscillate at 10 MHz while the output was banging against the rails.

p.p.s I blew out one of the LH0032's by shorting its output. The output of the LH0032 is not current limited and is the pin between the power pins.
When I blew the LH0032 I saw the bench power supply current go way up. I knew immediately what I had done. I was so mad that I had destroyed this expensive part that I flipped off the power to the circuit, grabbed the LH0032 and pulled it out of the socket. It was so hot it branded my thumb and index finger.

 

OK, I think I am going to make a J-FET input for the current feedback op-amp I have.
I just got done matching some FET's -- what a pain in the a**.
I will do a SIP with the EL2030, feedback resistors and the J-FET's. I doubt it will make much difference except for my not having to worry about the effects of bias current while testing.

Here is a simulation I did. Note that once the stray capacitance is charged the FET's are fast. The delay of the ET's is only about 1 ns. I can live with that right now since the CFB op-amp is much more than that. I contrast, look at what a "real" op-amp can do. Only about 1ns of delay for the gain of 2 buffer for the ADA4817.

 

@tindel I have built the J-FET buffer driving the EL2030 CFA op-amp onto a perf board. It works OK at "only" 10 MHz.* I will be wiring into the function generator later today or tomorrow.

* There does seem to be a low level oscillation at 200 MHz. I am asuming that this is due to poor layout on the SBB and lack of bulk bypass caps. Even if the 200 MHz remains, I think it is at too high in frequency and too low in amplitude to be a severe problem.

 

This is terribly interesting stuff. So did you notice improvements in performance with the addition of the j-FET buffer? The simulation doesn't show much improvement between the FET buffered stage and the unbuffered stage - but the power supply doesn't have any resistance to it either. My intent was to try to encourage you to stay with the CFA to achieve less ringing. The buffer would reduce loading of the drive circuitry, and provide a low enough output impedance to the CFA.

I've simulated the circuit using the EL2030 - prop delay is only 2.5ns - is that fast enough for you? The simulated ringing is awful, but a more modern CFA like the AD8007 would probably solve the ringing for you. I got the EL2030 model from the Intersil datasheet - had to make a few tweaks to get it to work, but now it works. I also added a couple resistors to the jFET buffer (as you'll see) to try to reduce the current in the buffer. Of course this effects the drive current, and hence, the prop delay as well. I wish I wasn't so lazy as to not dig up the AD8007 spice model and drop it in there. Maybe I'll do that next.

 

This is terribly interesting stuff. So did you notice improvements in performance with the addition of the j-FET buffer? The simulation doesn't show much improvement between the FET buffered stage and the unbuffered stage - but the power supply doesn't have any resistance to it either. My intent was to try to encourage you to stay with the CFA to achieve less ringing. The buffer would reduce loading of the drive circuitry, and provide a low enough output impedance to the CFA.

I've simulated the circuit using the EL2030 - prop delay is only 2.5ns - is that fast enough for you? The simulated ringing is awful, but a more modern CFA like the AD8007 would probably solve the ringing for you. I got the EL2030 model from the Intersil datasheet - had to make a few tweaks to get it to work, but now it works. I also added a couple resistors to the jFET buffer (as you'll see) to try to reduce the current in the buffer. Of course this effects the drive current, and hence, the prop delay as well. I wish I wasn't so lazy as to not dig up the AD8007 spice model and drop it in there. Maybe I'll do that next.

I built the FET and the EL2030 with the 2 510 ohm resistors onto a small perf-board. I haven't seen any obvious improvements so far. I just assume that the FET's will get rid of bias current problems downstream... see bad news below.

2.5ns? Really? I need to see what I am getting on my soldered circuit. If it is that fast then it will work on the SBB. Way, way to slow for the final 100MHz circuit. But -- that's the least of my worries right now. The plan is to use the OPA653 when I make a PCB for the 100MHz function generator's triangle/square oscillator.

The ringing seems to be really bad. I chose 510 ohms for the resistors on the perf-board to have maximum bandwidth at the expense of ringing and overshoot. Maybe I should have accepted lower bandwidth.

Thanks for the model.

I don't need no stinking resistors. I hand selected the 2N3819's to have an Idss of about 7.5ma. In practice there is an input to output offset of about 100mV. Larger than I expected from my screening, but tolerable.

Don't waste any of your time chasing down models unless I specifically ask. On the other hand, I just happen to have some models for the OPA653 and OPA659 that I don't know how to get working. (See attachments. )

The bad news is the oscillation is back with a vengeance. About 235MHz on the timing cap. This barely gets through the FET/EL2030 buffer. The buffer is so bad that this is the least of my worries. I first thought that the J-FET was oscillating so I added a 51 ohm resistor between the current sources and the gate of the input FET. No improvement. OK, I thought, then, it must be the EL2030 oscillating from seeing too much load capacitance. I put a 10 ohm resistor in series with the output pin. Still no change in the oscillation. My best guess right now is that the current source or the 2N3640's in the current switch is oscillating. More likely the 2N3640's because of the relatively low frequency.


p.s. I just realized that 235MHz on the 91pf timing cap seems like a lot. Some of the oscillation must be on my ground.