Given the dynamic characteristics of a recommended power on sequence and the steady state current draw, how does one estimate inrush? for example an IC takes VCORE of 1.2V, then 1.8V, and the 3.3V rail each separated by 20 ms.
The operating requirements are I=490mA max for VCORE, 2mA for 1.8V (IO) and analog (3.3V) is 315mA. I know sequencing minimizes inrush but how does one estimate inrush so as to properly design the power supply? The device is not totally a FPGA but one can extend the process for a FPGA. Most of what I read has not explained how to estimate. Is it device specific and if the manufacturer doesn't have the information how does one develop the estimation? Thanks

 

The sequencing is not to minimize an IC's inrush current, which is rather negligible for a multi-voltage chip. The sequencing most likely 1) permits an orderly startup (eg. brains before muscles) so the I/O isn't crazy as the core starts, and 2) prevents power boundary cross conduction that might occur due to intrinsic diodes in the part. The biggest concern at power application is charging all the supply bypass and filtering caps around the IC. Here the equation I=C * (dv/dt) applies. Usually there is a minimum dv/dt required for proper part/system startup, and a minimum recommended amount of capacitance on the part's rails. Combine those and you know the current needed from the supply at startup. Don't forget to add in the capacitance of the supply's output filter cap as well, it needs to be charged at the dv/dt rate as well. I make allowances for parts having tolerances that can increase the capacitance over nominal, then add in 10-20% margin to the resulting current calculation. If the C * (dv/dt) current is less than the rated part max, just go with the part max number and feel justified, else choose what gets you started quick enough. [Note: the part's max I/O supply current number does not account for loads added by you, so the true I/O max could be much more than shown on an IC's data sheet.]