Its a bad practice, depending on how power is removed from a circuit,
to tie large caps onto CMOS input pins. Reason, when power supply collapses
the Cap has to discharge thru parasitic diodes in CMOS input and you can create
localized hotspots on the die which are destructive. Simple fix is between
Cap and CMOS input put a small R to limit power down current. Size
for datasheet spec (if there is one, sometimes referred to as injection current),
or if no spec available limit to a few mA.


Regards, Dana.

 

Its a bad practice, depending on how power is removed from a circuit,
to tie large caps onto CMOS input pins. Reason, when power supply collapses
the Cap has to discharge thru parasitic diodes in CMOS input and you can create
localized hotspots on the die which are destructive. Simple fix is between
Cap and CMOS input put a small R to limit power down current. Size
for datasheet spec (if there is one, sometimes referred to as injection current),
or if no spec available limit to a few mA.


Regards, Dana.

To what circuit are you referring?

eT

 

For my circuit, just add a 10k ohm resistor in series with the parallel input to each gate.

 

To what circuit are you referring?

eT

Circuit posted earlier -