As per duality theorem, the expression remains valid, if AND<-> OR and 1<-> 0.
If F=x+yz+x'z , the applying duality principle, F= x(y+z)(x'+z). if I try to fill function in truth table, considering first expression as F1 and second one as F2, and using what I have understood, for F1 , RHS will give output as 1 and for F2 , output will be 0. But I am not getting F1 =F2. whereas Duality principle results in correct result for y( evaluated as y='1')= ab+bc+ca and y ( here y='0')=(a+b)(b+c)(c+a). Where am I going wrong?
x y z F1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1


x y z F2
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

 

But F1 isn't equal to F2, it is the dual of F2. One is positive logic and the other is negative logic.

Go through both tables and, in the table for F1, replace 0 with F and 1 with T since F1 is positive logic.

Now go through F2 and replace 0 with T and 1 with F since F2 is negative logic.

Now compare them.

 

But F1 isn't equal to F2, it is the dual of F2. One is positive logic and the other is negative logic.

Go through both tables and, in the table for F1, replace 0 with F and 1 with T since F1 is positive logic.

Now go through F2 and replace 0 with T and 1 with F since F2 is negative logic.

Now compare them.

Thank you so much WBahn. Your answer made me research more for positive and negative logic. I now understood positive and negative logic are dual for each other. And what I was doing earlier was giving dual of the function and not the function itself.
Further searching, I came to know what a self dual function is and F1=F2 iff it was a self dual function.

Thank you once again.

 

My pleasure.

Understanding logic duality can be quite useful when designing digital circuits since it can result is smaller, faster logic designs. Even better is to keep in mind that you, as the designer, generally have the choice of whether to make individual signals and/or various portions of your circuit positive logic or negative logic. This can significantly reduce your circuit's footprint, especially if you are implementing it using SSI logic gates.