Hi
i am working on 65nm CMOS process. I want to find the Drain and Gate capacitance. I am simulating s parameters. from Z11img (at gate side) and Y11img (drain side). but the values for the transistor size 24.48um claimed in one paper is 20fF (drain) and 30fF (gate) whereas my calculated values are 9fF and 22.6 fF respectively. The setup that i am using for measuring capacitanes (drain) is below:
Kindly guide to find proper value.
Thanks
i am working on 65nm CMOS process. I want to find the Drain and Gate capacitance. I am simulating s parameters. from Z11img (at gate side) and Y11img (drain side). but the values for the transistor size 24.48um claimed in one paper is 20fF (drain) and 30fF (gate) whereas my calculated values are 9fF and 22.6 fF respectively. The setup that i am using for measuring capacitanes (drain) is below:
Kindly guide to find proper value.
Thanks
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