Right now, I'm looking at http://www.allaboutcircuits.com/vol_3/chpt_3/10.html . The second example (OR gate,) seems to make sense, but the first example (AND gate,) is not making so much sense. How is it that closing the 'A' switch prevents any voltage from appearing at the output? Don't parallel branches all get the same source voltage? And what role does the resistor play in all this? Thanks for your time.

 

You will note the AND and the OR are very similar, since they are just inverted from + to - . If a diode is not connected to a voltage (and 0V is a voltage) it is out of the circuit. Visualize a variable power supply connected to each input.

 

When one of the input switches is closed, it sinks current from the pull-up resistor via the diode.

The pull-up resistor limits the current flow through the diode.

The output will measure roughly 0.6v, or the forward voltage of the diode when current is flowing through it.

 

I'm still not sure about this. Looking at the OR gate, the positive current flowing past the output is enough to raise it to a logical 1. Why is it not so for the AND gate?

 

With the AND gate, the switch shorts to ground.

With the OR gate, the switch shorts to V+.

In both cases, most of the supply voltage is dropped across the resistor when one of the switches is closed. The remainder (about 0.6v-0.7v) is dropped across a diode.

 

I understand that much but it just doesn't seem to add up in my mind. When in the OR gate the diode shorts to V+, the current merely passing the output raises it to a logic 1. When in the AND gate the diode shorts to GND, that same V+ is still passing the output. I'm not understanding how it's any different.

 

Nevermind, I think I get it now