I was reading the data sheet for 1N4007 (http://www.diodes.com/datasheets/ds28002.pdf) and I noticed that the values for the currents (peak forward surge and reverse) are given for resistive and inductive loads only. For capacitive loads, they require a 20% derating. What is the reason for this? Does it have something to do with the p-n junction? I thought that the diode currents are purely a function of the applied voltage and their extremal values should not depend on the connected load. What's missing here?

 

Could it have anything to do with a fully discharged capacitor looking like a short?

 

Could it have anything to do with a fully discharged capacitor looking like a short?

I don't see how the external circuitry used to measure max currents can affect said currents. Simply put, for a given current I, the diode requires a voltage drop V(I) (as complex as it can be), thus the power dissipated is I*V(I) and that should determine the max allowed current. It should have nothing to do with the load used to generate the current. The only thing I could fathom is that when connected to a capacitor, there could be charge leakage into the p-n junction, which in turn changes something, but this is pure speculation. I'd really love to learn the reason behind this derating!

 

ELI the ICE man. With an inductive circuit, current will build from zero to max over a period of time based upon the inductor value and resistance. In a capacitive circuit, current will be at its highest value and fall off as the capacitor charges. Again, assumption is that the cap is at zero state of charge.

 

ELI the ICE man. With an inductive circuit, current will build from zero to max over a period of time based upon the inductor value and resistance. In a capacitive circuit, current will be at its highest value and fall off as the capacitor charges. Again, assumption is that the cap is at zero state of charge.

Actually, not completely true since the resistance of the diode combined with the reactance of the capacitor will produce a voltage-current shift other than Pi/2 for sine input voltages (which is what they use in the datasheet). Anyway, this is neither here nor there since the actual shift will depend on the actual capacitance, which begs the question how they came up with the 20% degrading and how does it depent on the actual external capacitor.

 

Actually it is true. There is no resistive component from the diode, and there is no 90 degree shift. Don't look at this circuit in the frequency domain, look at it in the time domain.

In a typical (non -switcher) power supply when each cycle/half cycle there is a surge of current into the filter cap.

 

Sorry ErnieM but diodes have a significant resistive component from the leadwires to the silicon die and also from the conductivity of the silicon itself.

This is seen as the "softness" of the Vf "knee". Many power diodes will start conducting at 0.5v Vf, but will be at 1.5v or even 2.0v Vf by the time they are conducting at their max rated DC current.

The datasheet reference to "capacitive loads" simply implies cases where the conduction angle is very low and peak currents are very high, and the derating is needed specifically because of the diode's resistance and I squared R issues.