Digital Circuits

Thread Starter

menewbie

Joined Jan 31, 2006
34
Hi, I am using Spectre, a CAD tool that can simulate analog circuits, to simulate the control logic(the one that I have designed) of a 3-bit ADC. Spectre doesnt have basic logic circuits, like AND, OR gates, so I have to build those logic circuits using transistors. For example, for the NAND gates, I connected two NMOS in series and two PMOS in parallel. I also built different types of flip-flops.

The problem is when I simulated the control logic of a 3-bit ADC, Spectre gave me a result that was different than the one that was produced by Quartus II 4.0 (Quartus is CAD tool that has basic logic circuits). Quartus II gave me the right result, which was the result that I want.

I have already checked each one of the basic logic circuit that I have built and they all work fine. It's just that when I connect them together, the result becomes wrong. Why is this??

Btw, I have already tried putting a voltage buffer after the output of the gate to make sure that the logic gate that I have built can drive a large capacitive load.
 

windoze killa

Joined Feb 23, 2006
605
Originally posted by menewbie@Mar 6 2006, 07:24 PM
Hi, I am using Spectre, a CAD tool that can simulate analog circuits, to simulate the control logic(the one that I have designed) of a 3-bit ADC. Spectre doesnt have basic logic circuits, like AND, OR gates, so I have to build those logic circuits using transistors. For example, for the NAND gates, I connected two NMOS in series and two PMOS in parallel. I also built different types of flip-flops.

The problem is when I simulated the control logic of a 3-bit ADC, Spectre gave me a result that was different than the one that was produced by Quartus II 4.0 (Quartus is CAD tool that has basic logic circuits). Quartus II gave me the right result, which was the result that I want.

I have already checked each one of the basic logic circuit that I have built and they all work fine. It's just that when I connect them together, the result becomes wrong. Why is this??

Btw, I have already tried putting a voltage buffer after the output of the gate to make sure that the logic gate that I have built can drive a large capacitive load.
[post=14706]Quoted post[/post]​
What are you trying to drive? Are these standard logic gates? What types are you trying to combine? Can you supply schematics of each section and overall circuit?
 

n9352527

Joined Oct 14, 2005
1,198
I second Windoze suggestion, please post your complete transistor level control circuit (preferably without the buffers). There is no reason why it shouldn't work, unless there is an obscure error or something amiss somewhere.
 

windoze killa

Joined Feb 23, 2006
605
Originally posted by n9352527@Mar 6 2006, 09:06 PM
I second Windoze suggestion, please post your complete transistor level control circuit (preferably without the buffers). There is no reason why it shouldn't work, unless there is an obscure error or something amiss somewhere.
[post=14711]Quoted post[/post]​
I have never heard of Spectre but we use Quartus II at work (not me personally) and the engineers that use it think it is great and I feel that I would tend to trust it best.
 

n9352527

Joined Oct 14, 2005
1,198
Originally posted by windoze killa@Mar 6 2006, 11:36 AM
I have never heard of Spectre but we use Quartus II at work (not me personally) and the engineers that use it think it is great and I feel that I would tend to trust it best.
[post=14712]Quoted post[/post]​
They are different tools for different purposes. Spectre is part of Virtuoso package from Cadence. It is an analogue and mixed-mode simulation tools, which is an extended version of SPICE. Although it is designed for analogue circuits, it could also be use to simulate digital circuits at transistor-level, afterall a digital circuit is actually an analogue circuit with predefined voltage level presenting particular data. This is why it doesn't have any digital cell.

Quartus, on the other hand, is a digital only design/simulator tool with predetermined technology mapping where the timing and other parameters are already fixed. The design is entered at gate-level (digital cell).

As the design entry is different, the simulations are not comparable. You could easily make a mistake in entering the SPECTRE netlist, because handling so many transistors and parameters are error prone.
 

Thread Starter

menewbie

Joined Jan 31, 2006
34
Originally posted by n9352527@Mar 6 2006, 10:06 PM
I second Windoze suggestion, please post your complete transistor level control circuit (preferably without the buffers). There is no reason why it shouldn't work, unless there is an obscure error or something amiss somewhere.
[post=14711]Quoted post[/post]​
Thank you for the reply. I have attached the schematic of the control logic. That along with all the gates and the flip flops that I have build.

In the file control_logic, the little block that has light green text l (it is actually an i but looks like l) is the inverter. The big block is Tflipflop and has the light green text TflipflopCP.

In the file control_logic B, the big block on the top right-hand corner is Dflipflop.
 

Thread Starter

menewbie

Joined Jan 31, 2006
34
I think the problem comes from the structure of the D-flipflop. I tried to use another type of D-flipflop and it almost worked. Out of the three signals that I am comparing, two of them matched to the Quartus II.
 

Thread Starter

menewbie

Joined Jan 31, 2006
34
Originally posted by n9352527@Mar 6 2006, 10:06 PM
I second Windoze suggestion, please post your complete transistor level control circuit (preferably without the buffers). There is no reason why it shouldn't work, unless there is an obscure error or something amiss somewhere.
[post=14711]Quoted post[/post]​
You are right. The reason it didnt work is because in the AND3 file, I didnt put an inverter in front of NAND gate. Sorry for wasting your and Windoze Killa's time....
 

windoze killa

Joined Feb 23, 2006
605
Originally posted by menewbie@Mar 7 2006, 07:17 PM
You are right. The reason it didnt work is because in the AND3 file, I didnt put an inverter in front of NAND gate. Sorry for wasting your and Windoze Killa's time....
[post=14740]Quoted post[/post]​
No time wasted. It helps all our brains trying to sort these things out.
 

n9352527

Joined Oct 14, 2005
1,198
Originally posted by menewbie@Mar 7 2006, 09:17 AM
You are right. The reason it didnt work is because in the AND3 file, I didnt put an inverter in front of NAND gate. Sorry for wasting your and Windoze Killa's time....
[post=14740]Quoted post[/post]​
... and it is wonderful that you found out the mistake yourself. Troubleshooting is an art and you are well on your way on that...
 
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