Hi Guys,

Im studying for an electronics exam and I came past a question which I have started but finding it hard to finish.
The question is
Design a sequential circuit with two JK flip-flops, A and B, and two inputs, E and x. If E = 0, the circuit remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E = 1 and x = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01 back to 00, and repeats.

I have created the truth table which I have attached.

Im not sure How to get the equations to create the circuit.

Please help?

 

Hi Guys,

Im studying for an electronics exam and I came past a question which I have started but finding it hard to finish.
The question is
Design a sequential circuit with two JK flip-flops, A and B, and two inputs, E and x. If E = 0, the circuit remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E = 1 and x = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01 back to 00, and repeats.

I have created the truth table which I have attached.

Im not sure How to get the equations to create the circuit.

Please help?

So you have an up / down counter made with J-K flip flops and no clock pulse, just the E and x inputs?
Are other gates allowed?
Look at the design of other chips that are up / down counters.

 

Hi Guys,

Im studying for an electronics exam and I came past a question which I have started but finding it hard to finish.
The question is
Design a sequential circuit with two JK flip-flops, A and B, and two inputs, E and x. If E = 0, the circuit remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E = 1 and x = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01 back to 00, and repeats.

I have created the truth table which I have attached.

Im not sure How to get the equations to create the circuit.

Please help?

Your table looks good.

The next step is to make an excitation table in which you lay out all of the state variables and input variables as inputs and then list all of the needed outputs (with two JKFFs, you have four such outputs -- the J and the K for each FF).

After that it is simply a matter of determining the equation/circuit for each output.

 

So you have an up / down counter made with J-K flip flops and no clock pulse, just the E and x inputs?
Are other gates allowed?
Look at the design of other chips that are up / down counters.

It's a sequential circuit and the table is laid out along the normal lines for a clocked circuit. The presence of a free-running clock is implied.

Most counter chips are going to have a lot of additional functionality and are not going to be represented using JKFFs, so they will be of limited utility for his needs.

Better to just knuckle down and design the circuit based on the desired behavior instead of trying to adapt someone else's design.

 

Your table looks good.

The next step is to make an excitation table in which you lay out all of the state variables and input variables as inputs and then list all of the needed outputs (with two JKFFs, you have four such outputs -- the J and the K for each FF).

After that it is simply a matter of determining the equation/circuit for each output.

How would you go about creating the excitation table as I am not exactly sure?

 

Okay, input is an enable. x is an up / down input. No clock!!!

 

The presence of a free-running clock is implied.

No, it isn't.
x is direction and E is the clock.
When x = 0, count up.
When x = 1, count down.
Counting occurs on the positive edge of E.

ak

 

No, it isn't.
x is direction and E is the clock.
When x = 0, count up.
When x = 1, count down.
Counting occurs on the positive edge of E.

ak

Okay, that works.
So A toggles every clock pulse whether you are going up or down, and B toggles every other clock pulse. Counting up B toggles if A is set. Counting down B toggles if A is clear.
Put that into a truth table and schematic.

 

A few minutes with google would have lead you to this page. You would have to modify the three bit asynchronous up/down counter to suite your needs.

 

x is direction and E is the clock.
When x = 0, count up.
When x = 1, count down.
Counting occurs on the positive edge of E.

I interpreted the problem as having direction control (x) and an enable (E). When enable is is LOW, the counter doesn't increment regardless of whether the clock is stopped.

 

I grudgingly concede that E *might* stand for Enable, but assuming an invisibe clock signal is, well, an assumption. The core of the circuit is identical either way, only 1 AND gate difference.

ak

 

I interpreted the problem as having direction control (x) and an enable (E). When enable is is LOW, the counter doesn't increment regardless of whether the clock is stopped.

Same here, as in 74190, E is Enable. But it can work as the Clock input with J and K tied high on the A latch. Since a circuit has already been suggested, here is a modified 74190 version I had in mind.

.I haven't tried to simulate it yet. There was no point since a similar circuit was already presented.

 

No, it isn't.
x is direction and E is the clock.
When x = 0, count up.
When x = 1, count down.
Counting occurs on the positive edge of E.

ak

E being the clock is not consistent with the spec: "When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats."

How is it doing this with E being held at a static value of 1?

Further, look at the state transition table he prepared in the first post. E is a count enable (hence 'E').

 

How would you go about creating the excitation table as I am not exactly sure?

First, please clarify whether or not you have a separate clock signal for your system.

The excitation table is very straight forward.

Say, for example, you have two inputs 'a' and 'b' and you have one flip flop whose output if 'Q'. For each combination of inputs you know what you want the next value of Q to be. So you just use that information to determine what you need the values of J and K to be for each combination of those three things. That's your excitation table.

 

Okay, input is an enable. x is an up / down input. No clock!!!

Gee, go look at the Wikipedia article for the excitation tables for the common flip flops. Not once do they mention a clock. Guess they think that standard flip flops don't have clocks!

The presence of a free-running clock signal is so ubiquitous with sequential logic that is assumed to exist. If it doesn't, THAT is when something needs to be said (such as the circuit is an asynchronous sequential circuit).

 

How would you go about creating the excitation table as I am not exactly sure?

Look at the table attached to this post. It's for different problem, but it uses JK flip flops with a control line so the steps are similar.

 

There is an alternative to excitation tables which may be called 'transition mapping' for sequential logic design. I have not seen it described in any textbook, but I have a few notes from a graduate computer course back in 1975. First, the transitions are generated from the state table for each state variable that will be represented by a JK flip-flop according to the following rules for the 4 possible transitions:

0→0=0, 1→1=1, 0→1=α, 1→0=β

Then these transitions are plotted on a Karnaugh Map to obtain the J & K logic expression for each flip-flop as follows:

J: α {β,1} Alpha required; Beta & One optional (don't care)
K: β {α,0} Beta required; Alpha & Zero optional (don't care)

This is so simple that I am able to program a spreadsheet to generate the transition table from the state table, and automatically generate the K-map & plot the transitions. Plugging the state table for this problem into the spreadsheet gives the JK Karnaugh maps for each flip-flop on which I have indicated a possible logic simplification. Note that I have not checked this solution for correctness but it should be simple to do in a logic simulator.