Design of a two stage CMOS op-amp on LTspice

Thread Starter

Alexx98

Joined Nov 5, 2017
30
Hello,

I am currently working on an amplifier design, and I don't know how to find power consumption on LTspice program. I am asked to find the voltage gain > 60dB, phase margin > 60deg, power consumption and also bandwidth (unity gain) >150MHz


schematic.png

I used 180nm technology so that I took W/L ratio's as follows:
M1=M2=M5=M8: 0.36u/0.18u
M3=M4: 5.4u/0.18u
M7: 0.72u/0.18u
M6: 34.2u/0.18u
I also have problem about the gain and phase margin. When I run AC simulation it gives me negative output. How can I fulfill all these requirements?

simulation.png result.png
 

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crutschow

Joined Mar 14, 2008
26,348
I don't know how to find power consumption on LTspice program
Do a transient simulation.
Position the cursor over V1.
Press the ALT button and then the left mouse button.
The plot will now show the power generated by V1, which is the power consumed by the circuit.

Alternately do a DC op pnt simulation, and then multiply the displayed V1 current times the V1 voltage.
When I run AC simulation it gives me negative output.
Your inputs are biased at ground.
Add a DC bias to V2 and V3.
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
Do a transient simulation.
Position the cursor over V1.
Press the ALT button and then the left mouse button.
The plot will now show the power generated by V1, which is the power consumed by the circuit.

Alternately do a DC op pnt simulation, and then multiply the displayed V1 current times the V1 voltage.
Your inputs are biased at ground.
Add a DC bias to V2 and V3.
Thank you so much. But still I can not display the power :/
s.png
 

Jony130

Joined Feb 17, 2009
5,213
Did you "design" this amplifier by yourself?
How did you expect that this circuit will work from a single supply without any negative feedback loop?
Did you ever use in real life an op amp?
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
Did you "design" this amplifier by yourself?
How did you expect that this circuit will work from a single supply without any negative feedback loop?
Did you ever use in real life an op amp?
Of course I didn't 'design' this amplifier by myself. It is taken from Sedra's book.
Yes, I think it can, since this requirement is also given by the instructor. There is no negative supply, rail-to-rail voltage is between 0 and 1.8 V.
Also, I didn't use an op amp until now because I am currently learning it in University and I don't understand if you are not really interested in the question why you are asking those judgmental questions.
 

Jony130

Joined Feb 17, 2009
5,213
Your circuit will never work properly with a single supply if you do not add a bias voltage at the input (0.5Vdd) or even some DC negative feedback.

Of course I didn't 'design' this amplifier by myself. It is taken from Sedra's book.
So you also copy W/L ratios from the book?
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
Your circuit will never work properly with a single supply if you do not add a bias voltage at the input (0.5Vdd) or even some DC negative feedback.


So you also copy W/L ratios from the book?
No, I didn't copy from there. I've read several articles about this circuit and also I gave some numbers to increase the gain. I will put a DC source to the input then. Thank you
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
Your circuit will never work properly with a single supply if you do not add a bias voltage at the input (0.5Vdd) or even some DC negative feedback.


So you also copy W/L ratios from the book?
power.png
I add dc voltage 0.9V to the input and did .op analysis and multiplied the current through the V1 source and V1, is it correct?
 

Jony130

Joined Feb 17, 2009
5,213
All I can say is that you need to recalculate the W/L ratios. And your MOS model is not fully compatible with LTspice.
And I'm not an LTspice guru to help you with this compatibility problem.
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
All I can say is that you need to recalculate the W/L ratios. And your MOS model is not fully compatible with LTspice.
And I'm not an LTspice guru to help you with this compatibility problem.
Okay, I understand. Thank you so much for your help!!
 

crutschow

Joined Mar 14, 2008
26,348
Running open-loop, the op amp output is saturated at 0V.
You can add negative DC feedback to bias the op amp in its active region.
That is provided below by the addition of R1 and C2, which act as low-pass filter feedback giving a DC gain of 1.
Their RC time-constant value is very large so the AC response is not affected.
This gives an op amp gain of over 120dB @ 1Hz with the expected 20 db/decade rolloff due to Co.

upload_2018-12-30_0-32-24.png
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
Running open-loop, the op amp output is saturated at 0V.
You can add negative DC feedback to bias the op amp in its active region.
That is provided below by the addition of R1 and C2, which act as low-pass filter feedback giving a DC gain of 1.
Their RC time-constant value is very large so the AC response is not affected.
This gives an op amp gain of over 120dB @ 1Hz with the expected 20 db/decade rolloff due to Co.

View attachment 166706
Result.png

I am still having a gain of 35dB, which is probably because of the W/L ratios. I will change them to increase the gain and have a phase margin of 60degrees. Thank you!
 

Thread Starter

Alexx98

Joined Nov 5, 2017
30
From what I see you have ignored the 180nm lib. So you are using the ideal MOS model without even including channel length modulation.
What should I do in this case? How can I include the effect of channel length modulation to the circuit?
 
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