I see it!


got the column 11 och 10 of b,a wrong!
Sweet, otherwise all correct I guess, thank you very much! Now I shall try to make the circuit work on a breadboard

 

Great! I learned about Logisim. Probably the last person on the planet not to know about it.

 

Another question about the K-map, if the state 11 is regarded as a forbidden state, can I then put don't care conditions on the row 11 of q1q0? Like this:

The functions gets minimized quite a bit then. I am using D Flip Flops btw.

 

I guess my question is what do you mean by "forbidden state"? Perhaps you can change your state diagram to show what is meant? My suggestion would be to always go back to the state diagram when making changes. Then, go forward again. I think making changes at the K-map stage is not clear and error prone.

There are ways to perform state minimization which can save logic but that is a relatively complicated step. The other thing is to look for common minterms between the k-maps. I don't see any.

I would be interested in your "forbidden state" step. Maybe I can learn something!

 

I guess my question is what do you mean by "forbidden state"? Perhaps you can change your state diagram to show what is meant? My suggestion would be to always go back to the state diagram when making changes. Then, go forward again. I think making changes at the K-map stage is not clear and error prone.

There are ways to perform state minimization which can save logic but that is a relatively complicated step. The other thing is to look for common minterms between the k-maps. I don't see any.

I would be interested in your "forbidden state" step. Maybe I can learn something!

I guess I have already done the don't care conditions when assigning the next state, for example input a could be ba or !ba. But I thought if it is a rule of thumb to simply put don't care on the state 11 since that one is not obtainable with a D Flip Flop since the input is inverted and can only become 10 or 01 with one input D. But I am not sure about this...

 

This is what I got, what do you think? The muxes are a 8 to 1 mux on the breadboard but Logisim seems to not allow 3 select inputs so I split it into multiple 2 to 1 muxes.

 

I cannot understand this schematic. Can you do it just with standard sum-of-products form. AND and OR gates and put on some net labels? Why muxes?

 

I cannot understand this schematic. Can you do it just with standard sum-of-products form. AND and OR gates and put on some net labels? Why muxes?

I used muxes because the gates in our lab-kit were not enough, but sure, I'll make a new one with AND and OR gates

 

kind of chaotic

 

View attachment 224424
kind of chaotic

Not chaotic. It's beautiful. Your layout is very clear. Does it work?

 

Not chaotic. It's beautiful. Your layout is very clear. Does it work?

Nope, I have been trying all day. Trying to go through it slowly step by step...
It works great with logisim...

 

Nope, I have been trying all day. Trying to go through it slowly step by step...
It works great with logisim...
View attachment 224459

There is at least one error in your "all gates" schematic. It goes not match the minterms in the k-maps and is different than the "gate and mux" schematic. I strongly suggest adding net names. It looks like some confusion between the q0 and q1 outputs.