Depletion-load NMOS NOR Gate analysis

Thread Starter

Ritu Deshpande

Joined Nov 21, 2018
Hi! I've been studying CMOS Logic circuits from the book "CMOS Digital Integrated Circuits Analysis and Design" - 3rd edition by Mo Kang and Yusuf Leblebici. Section 7.2 of this book deals with the analysis of a two-input NOR gate that has a depletion-load design. Equation 7.1 of this equation gives the drain current of the depletion-load. This equation differs from the general equation for drain current of a MOSFET. Capture1.JPG
The highlighted term in this equation has the product of the threshold voltage, Vt, and the output high voltage, Voh, which, I suppose is incorrect. The general equation for drain current in linear region of a MOSFET has the difference between gate to source voltage and threshold voltage, Vgs-Vt, instead. I've attached a snap of the book for reference. Thanks for the help!