Delaying an output

Thread Starter

lokgotkent

Joined Sep 22, 2010
7
I understand that D-type Flip-Flop and Shift Register are used to "store" data, in the sense by delaying an output. However, they are either positively or negatively triggered. After looking at the waveforms of clock input and data input, I found the data output is not exactly the same as the data input. So my question is, how could I "modify" the input to give the same waveform for exactly n seconds? Thanks!
 

beenthere

Joined Apr 20, 2004
15,819
Can you provide an illustration of the failure of either device's output to agree with the input?
I understand that D-type Flip-Flop and Shift Register are used to "store" data, in the sense by delaying an output. However, they are either positively or negatively triggered.
The data is stored indefinitely, once it has been clocked into the register, so long as power is maintained and no further clocks occur. What significance do you place on the polarity of the clock pulse or the delay between the clock pulse and the output changing to agree with the input?
 
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