Unless I am misunderstanding it, the CLC capabilities of the PIC micro controllers fall quite short of what I need to create this project. If I understand it right, there are 8 CLC blocks per processor and each one can only perform 2 gates of logic on 4 inputs with one output, or 1 bit of memory. That would require a LOT of PIC controllers side by side to accomplish the task.

Alternatively it looks like a Cypress PSoC has a much wider capability, but I really didn't understand what it did after paging through the datasheet.

The CLC is designed as a helper module for programming MCU logic, it in isolation won't be able to do the entire project but you should be able to reduce (simplify to table-driven codes) the real-time raw bit capture requirements to something easily within the interrupt ISR programming capability for setting motor phase shifts.

 

My guess is that the best options left to you are:

1. Discrete digital logic (synchronous, modify my circuit to include a clock)
2. FPGA

I always prefer sync to async, because it's far more predictable.

 

Hi nsaspook,

I tried to PM you this message, but the site told me I was not allowed to do so. I want to thank you for sharing your thoughts on my project over the past few days. I am really hoping to make this work and I really like your idea of using a PIC micro + CLC to do the job.

I wanted to ask if you'd be willing to mentor me through the project? My hope is to pick out the micro, design the circuit, get PCBs made, and actually program this thing to do what I need it to.

It's absolutely fine if you'd rather not be involved, but I'd greatly appreciate any assistance.

I will continue along with my discrete digital logic design in the meantime.

 

Hi nsaspook,

I tried to PM you this message, but the site told me I was not allowed to do so. I want to thank you for sharing your thoughts on my project over the past few days. I am really hoping to make this work and I really like your idea of using a PIC micro + CLC to do the job.

I wanted to ask if you'd be willing to mentor me through the project? My hope is to pick out the micro, design the circuit, get PCBs made, and actually program this thing to do what I need it to.

It's absolutely fine if you'd rather not be involved, but I'd greatly appreciate any assistance.

I will continue along with my discrete digital logic design in the meantime.

Sorry, I'm deep in actual work making a 32-bit motion tester prototype.
https://github.com/nsaspook/vcan

 

Sorry, I'm deep in actual work making a 32-bit motion tester prototype.
https://github.com/nsaspook/vcan

no worries! Appreciate the feedback thus far. Interesting project! I’ll have to read some more. Thanks for sharing!

 

Your taking an example from a Microprocessor app note, and doing this in hardware .
Why not stay with a micro , Something like the teenesy will do this easily.
600 MHz processor , https://www.pjrc.com/store/

Glad to see your now looking at using a clock, even if you are calling it an enable.

Decoding lie this is a synchronous design process s that decoding glitches are removed,


Do it in logic, an FPGA , a CPLD , a Micro, they are all synchronous design processes.
current state / next state decoding,

 

Your taking an example from a Microprocessor app note, and doing this in hardware .
Why not stay with a micro , Something like the teenesy will do this easily.
600 MHz processor , https://www.pjrc.com/store/

Glad to see your now looking at using a clock, even if you are calling it an enable.

Decoding lie this is a synchronous design process s that decoding glitches are removed,


Do it in logic, an FPGA , a CPLD , a Micro, they are all synchronous design processes.
current state / next state decoding,

oohh. I like those. At that price and size, I could solder it right onto a PCB that does the differential receiver/line driver plus level shifting.I didn’t know there we’re any low cost MCUs that had that kind of performance. I probably wouldn’t have any issue with reading the signals at that speed.

I almost wish that I had not started with Arduino. Really locks me into a mindset that I need 5V stuff that can be programmed with one tool that I know.

thanks for the idea! I’m going to order one now and see if I can get the motors running on a breadboard. And then i can build the PCB.

 

I almost wish that I had not started with Arduino.

Personally, I think that getting started with Arduino on the world of MCU's is a terrible idea. I think people should first get acquainted with the lowest level language for MCU's first before proceeding upwards. That is, get started learning at least some form of assembly code. That way the user gets a much better grasp of what MCU's can and cannot do. Whereas an Arduino is a black box in which easy code goes in, and easy functionality comes out. It never allows the user to learn the nuances of what makes a great project.

 

oohh. I like those. At that price and size, I could solder it right onto a PCB that does the differential receiver/line driver plus level shifting.I didn’t know there we’re any low cost MCUs that had that kind of performance. I probably wouldn’t have any issue with reading the signals at that speed.

I almost wish that I had not started with Arduino. Really locks me into a mindset that I need 5V stuff that can be programmed with one tool that I know.

thanks for the idea! I’m going to order one now and see if I can get the motors running on a breadboard. And then i can build the PCB.

Teensy is Arduino ,
Paul the designer is VERY involved in Arduino development,

Also regarding 5v,
I don't think any Arduino have been 5V IO for a good few years,
I think the Mega might have been the last that was,

 

In your first post, delaying the enable signal injects a phase delay between when the inputs are sampled and when the output is gated on. What is the maximum amount of time you can tolerate for that delay? The string of gates is a common fix (I've done it many times inside a CPLD, using macrocells as delay elements), but the delay value can change significantly with temperature.

If you can tolerate a lot of delay, one approach is to simply invert the enable signal between the input stage clock and the output stage enable. For example, if the enable signal is a 10 MHz symmetrical square wave (100 ns period), then the delay would be 50 ns and as steady as the characteristics of the signal.

ak

 

Personally, I think that getting started with Arduino on the world of MCU's is a terrible idea. I think people should first get acquainted with the lowest level language for MCU's first before proceeding upwards. That is, get started learning at least some form of assembly code. That way the user gets a much better grasp of what MCU's can and cannot do. Whereas an Arduino is a black box in which easy code goes in, and easy functionality comes out. It never allows the user to learn the nuances of what makes a great project.

I think I might have to agree. The low barrier to entry definitely got me drawn into Arduino when I first started, but the design tends to have you searching for the bits and pieces of your project online from people who have doen something similar and copying their code or downloading libraries. I never had to learn how to squeeze performance from a Micro, and I got very attached to the Arduino IDE and really didn't like the idea of learning another toolchain.

Teensy is Arduino ,
Paul the designer is VERY involved in Arduino development,

Also regarding 5v,
I don't think any Arduino have been 5V IO for a good few years,
I think the Mega might have been the last that was,

Interesting! I've only ever used the UNO and the MEGA. Most of the stuff I play with is 24VDC logic (industrial standard) so it is fairly easy to get level shifters from 5V to 24V and 24V to 5V. Did a little 3.3V stuff with a NodeMCU, but it was pretty much just reading a dry contact.

In your first post, delaying the enable signal injects a phase delay between when the inputs are sampled and when the output is gated on. What is the maximum amount of time you can tolerate for that delay? The string of gates is a common fix (I've done it many times inside a CPLD, using macrocells as delay elements), but the delay value can change significantly with temperature.

If you can tolerate a lot of delay, one approach is to simply invert the enable signal between the input stage clock and the output stage enable. For example, if the enable signal is a 10 MHz symmetrical square wave (100 ns period), then the delay would be 50 ns and as steady as the characteristics of the signal.

ak

I'm really working towards implementing fully clocked logic and this looks to be a great option. I assume you can use the original signal on the next set of flip-flops to add an additional delay?

I'm pretty damn close on the discrete digital design and I kinda want to finish it up. I will use your method for the delay.