Deep Reinforcement Learning for automated analog IC design sizing- Suggest me my path is right or wrong?

Dear Mentors, I'm a newbie in this research community, and I planned to do my research in the analog ic design sizing (front end) using optimization techniques, especially deep reinforcement learning. I need all your suggestions, whether my identified research gap can have much space to explore or you can suggest any right way to progress my research. Thanks in advance for all your suggestions. Your little information means a lot for me.