im not sure how to go about this problem, confused with working out the VG for Q1 and Q2. I know when normally working out the VG you would multiply Vdd with R2/R1+R2 (voltage divider) but im not sure what Resistance id use when in this scenario. And how you would draw the AC equivalent small signal model for this, im confused because the transistors are connected at the source and drain.??? can anyone please help???

 

What do you find confusing because the transistors are connected together?

Draw a box around each transistor -- there are three terminals where that circuit crosses the boundaries of the box. Now replace the contents of each box with the small signal model you are using, which also has three terminals where it crosses the box (four if your model happens to include the bulk bias connection, which it probably doesn't).

 

What do you find confusing because the transistors are connected together?

Draw a box around each transistor -- there are three terminals where that circuit crosses the boundaries of the box. Now replace the contents of each box with the small signal model you are using, which also has three terminals where it crosses the box (four if your model happens to include the bulk bias connection, which it probably doesn't).

ive attempted other questions that are similar, and in those the transistors are normally connected as for transistor 1's drain to transistor 2's gate, however in this example its source of Q2 transistor connected to the drain of Q1 transistor

 

ive attempted other questions that are similar, and in those the transistors are normally connected as for transistor 1's drain to transistor 2's gate, however in this example its source of Q2 transistor connected to the drain of Q1 transistor

So?

Your small signal model for Q2 has a terminal that is the source, right?

Your small signal model for Q1 has a terminal that is the drain, right?

Draw a wire between these two terminals.