DATAPATH OF MIPS's PROCESSOR

Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
Hello fellas!
I would like to ask how actually in the first step aka (IF) I fetch instruction and in the same time increasing the PC by 4? is it well synchronized in a proper way that once I finish the first stage, the PC's value will be added by one(4) and not having any faults? I'm a lil in doubt and looks weird because in the first stage they are two operations in parallel, one is fetching and the second one is adding PC by 4 ..
here's a link for datapath graph :
https://www.researchgate.net/figure/Addition-of-Pipeline-to-MIPS-Datapath_fig5_305724529
 

Papabravo

Joined Feb 24, 2006
16,967
If all the circuits on the datapath were combinatorial circuits that ran asynchronously then a potential problem called a race condition might occur. In the case of the MIPS processor, that is not the case. The small block labeled PC is actually a register whose contents are updated only on a particular clock edge. There is plenty of time for the register value to be presented to the ALU, for the the carry to propagate along the chain as the constant is added to the present value, and for the result to make it back to the inputs of the PC register where they will wait patiently for the arrival of the clock edge. When the clock edge arrives the data on the inputs will be loaded into the PC register and another instruction fetch can happen.

At this point you might want to ask what happens if the instruction is a 'JUMP' or a 'CALL'? When does the destination address get transferred to the PC? Are there instruction fetches that need to be discarded?
 
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Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
Does the PC's hardware read the data on buses simultaneously ? I mean lets assume I have address of 32bit and [0:15] bits are connected to specific element which reads data in general, then all 16 connected bit will be transmitted to the other hardware that they connect at? thanks.
 

Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
If all the circuits on the datapath were combinatorial circuits that ran asynchronously then a potential problem called a race condition might occur. In the case of the MIPS processor, that is not the case. The small block labeled PC is actually a register whose contents are updated only on a particular clock edge. There is plenty of time for the register value to be presented to the ALU, for the the carry to propagate along the chain as the constant is added to the present value, and for the reult to make it back to the inputs of the PC register where they will wait patiently for the arrival of the clock edge. When the clock edge arrives the data on the inputs will be loaded into the PC register and another instruction fetch can happen.

At this point you might want to ask what happens if the instruction is a 'JUMP' or a 'CALL'? When does the destination address get transferred to the PC? Are there instruction fetches that need to be discarded?
Thanks for ur illustration, for your question I reckon that they will be also arrived and wait patiently till the next edge comes for fetching new instruction..
 

Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
In addition, at the stage ID: INSTRUCTION DECODE, is the hardware named Registers FILE has an access to read the data at the register number of our input? for example, as what's shows in the link above (graph of datapath), the registerFile will read the data of the register number that we enter it on its inputs, it's weird if actually that hardware has access to the memory for getting the data of the register's number ...... as a result it would be appreciated if you guys illustrate that point(how actually RegisterFILE hardware device access the data of the register's number on its input)


thanks alot
 

Papabravo

Joined Feb 24, 2006
16,967
In addition, at the stage ID: INSTRUCTION DECODE, is the hardware named Registers FILE has an access to read the data at the register number of our input? for example, as what's shows in the link above (graph of datapath), the registerFile will read the data of the register number that we enter it on its inputs, it's weird if actually that hardware has access to the memory for getting the data of the register's number ...... as a result it would be appreciated if you guys illustrate that point(how actually RegisterFILE hardware device access the data of the register's number on its input)


thanks alot
There is a small circuit called a decoder. It takes some number of binary inputs like 3, or 4, or 5 and produces 2^3 = 8, or 2^4 = 16, or 2 ^ 5 = 32 unique outputs. These inputs are used as a register address. Each of those output will enable the register contents onto the bus for reading. The same decoder can be used in conjunction with a "Write enable" signal to write the contents of the bus back into the selected register. Main memory works the same way except there are more address inputs and more location so deal with.
 

Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
There is a small circuit called a decoder. It takes some number of binary inputs like 3, or 4, or 5 and produces 2^3 = 8, or 2^4 = 16, or 2 ^ 5 = 32 unique outputs. These inputs are used as a register address. Each of those output will enable the register contents onto the bus for reading. The same decoder can be used in conjunction with a "Write enable" signal to write the contents of the bus back into the selected register. Main memory works the same way except there are more address inputs and more location so deal with.
Fantastic!
may please another help? I'm totally always imagining it but I need to verify about that ..

once there's a number of register and I want to read it, I analog it to something like a tag (number of register) and its data like a page that the tag appointing on .... but I would like to ask how actually the register(number of register) and its data represented on memory?
is it like
yyyy: ((number of register))
xxxxxxxxxxxxxxxxxxxxxx ((data))
xxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxx

actually I'm asking how should I visualize that number of register and its data by the aspect of bits(bytes) ?

thanks
 

Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
what does it mean jump operation like jr $ra? does it mean really that hardware goes/jump to other location? it's really weird how hardware could jump :) ?
I ain't totally comprehend what does it mean "jump" by hardware aspects?!
 
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Papabravo

Joined Feb 24, 2006
16,967
what does it mean jump operation like jr $ra? does it mean really that hardware goes/jump to other location? it's really weird how hardware could jump :) ?
Not at all. The way to think of a "JUMP" or "CALL" instruction is that it computes a destination address, and then at the appropriate point in the instruction cycle, that address is "jammed" into the PC register. With this new address in the PC register the next instruction is fetched from the location that the PC register points to.
 

Thread Starter

FreddoAvishi

Joined Mar 8, 2019
36
Not at all. The way to think of a "JUMP" or "CALL" instruction is that it computes a destination address, and then at the appropriate point in the instruction cycle, that address is "jammed" into the PC register. With this new address in the PC register the next instruction is fetched from the location that the PC register points to.
Alright thanks :)
another lil question, I'm a lil perplexed on how processor can read "by one way/hand" a certain number of bits and not one by one respectively, so lets assume I have to read address of 32 bit, the processor can read it in one hand, how it's going on? isn't there a racing between bit and bit? I mean with racing, one bit arrived (read) before the other bit .. looks weird .. can you illustrate that point? or actually to give analogy to visualize how processor can read by one time 32bits

does the processor featured to read by one time a number of bits?
 
Last edited:

Papabravo

Joined Feb 24, 2006
16,967
Alright thanks :)
another lil question, I'm a lil perplexed on how processor can read "by one way/hand" a certain number of bits and not one by one respectively, so lets assume I have to read address of 32 bit, the processor can read it in one hand, how it's going on? isn't there a racing between bit and bit? I mean with racing, one bit arrived (read) before the other bit .. looks weird .. can you illustrate that point? or actually to give analogy to visualize how processor can read by one time 32bits

does the processor featured to read by one time a number of bits?
Again it is all about clocks. An address is presented to a memory device. Shortly after the first address bits are presented to the memory device a clock comes along which says: "no more changes on the address lines". Whatever bits were there are "latched" and the memory begins either a read or a write cycle. In a read cycle there is some period of time that must elapse before the data bits from the memory device will be valid. This time from "address bits stable" to "read data valid" is referred to as the "read cycle time". All the bits on the data bus are available in parallel and are stable and valid after the "read cycle time" has elapsed. Understanding how clocks are generated and distributed in a processor is essential to understanding the operation.
 
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