Hi all,

I have a 7474 positive edge triggered flip flop. At power up, I have the D input, ~PRE, and ~CLR all tied high. I need an initial low on the ouput Q. The output Q is high upon power up. The function of this circuit is to detect a positive edge that causes the output to go high and then quickly reset itself resulting in a glich that triggers the 556 timer. This event should happen on every positive edge on the clock input. How can I configure this to have an initial low at power up? The 10k resistor on the clock input is not in the circuit.

 

I'd omit the 7474 and Q2, put a series cap (~10nF) between Q1 collector and pin 2 of the 556, provide a pull-up (~10k) from pin 2 to Vcc, and drive R2 with the pressure sensor signal.

 

Using a FF output to clear itself is a really bad idea. Did you come up with it on your own or did you find it on the interwebs?

The switch will also cause the CLK input to bounce. Not a great idea.

 

I can't drive the timer with the pressure sensor signal because the pressure sensor signal stays high for a long period of time, hence the timer output stays high and I only need it to be high for a set interval of time.

This is just a use for a few weeks and pitch circuit for a special application. It doesn't have to meet any quality or regulatory standards. I just need something that works and I need it yesterday. I'll have to double check, but I'm pretty sure the pressure sensor switch is debounced. Are there any ideas of other ways to accomplish the same thing? Thanks for your responses.

 

Hi all,

I have a 7474 positive edge triggered flip flop. At power up, I have the D input, ~PRE, and ~CLR all tied high. I need an initial low on the ouput Q. The output Q is high upon power up. The function of this circuit is to detect a positive edge that causes the output to go high and then quickly reset itself resulting in a glich that triggers the 556 timer. This event should happen on every positive edge on the clock input. How can I configure this to have an initial low at power up? The 10k resistor on the clock input is not in the circuit.

Use a power on reset circuit connected to the CLR pin of the 7474. This can be a resistor and cap in series.

GND---C----+----R---VCC

On power up, the junction(+) will be at GND untill the cap charges. This will initialize the NotQ output high
which sets the Q output low.

eT

 

Or just capacitively couple the 555 input to your switch and be done with it. No need for complex solutions for simple problems.

 

I can't drive the timer with the pressure sensor signal because the pressure sensor signal stays high for a long period of time

That's why I suggested the series capacitor in post #2. Kubeek is saying the same thing.

 

Using a FF output to clear itself is a really bad idea. Did you come up with it on your own or did you find it on the interwebs?

.

Its done all the time with counter chains - which after all are a chain of flip-flops.

The circuit as shown will generate a narrow spike, width determined by the various propagation delays in the path.

I'd go for a delay driving the reset transistor, the power up state can be set by loading the reset pin at power up by a C/R network across the supply. Resistor summing ore diode-OR should be used to combine the PWR reset C/R and reset transistor pulse.

 

That's why I suggested the series capacitor in post #2. Kubeek is saying the same thing.

Understand, I'm just a lab tech, not an engineer. Can you explain how the series capacitor works in this instance?

 

Something along these lines should work http://forum.allaboutcircuits.com/attachments/555-edgetriggered-monostable-gif.18787/

 

Its done all the time with counter chains - which after all are a chain of flip-flops.

The circuit as shown will generate a narrow spike, width determined by the various propagation delays in the path.

I'd go for a delay driving the reset transistor, the power up state can be set by loading the reset pin at power up by a C/R network across the supply. Resistor summing ore diode-OR should be used to combine the PWR reset C/R and reset transistor pulse.

That has nothing to do with the advisability of doing it however.

 

That has nothing to do with the advisability of doing it however.

Tell that to whoever designed the 7490.

 

Tell that to whoever designed the 7490.

Probably why I never used one of those.
Actually the counter does not do that internally. It just has an asynchronous clear. It is possible to use an asynchronous clear without creating hazards. I still never had occasion to use one.

 

Can you explain how the series capacitor works in this instance?

The cap is normally in a discharged state. When the input transistor switches on, the left and right ends of the cap are pulled down and so is pin 2, triggering the 556. The cap quickly charges via the pull-up resistor on trigger pin 2, so pin 2 goes high again no matter how long the transistor stays on. When the transistor turns off, the cap discharges via the collector resistor and pull-up resistor.

 

The cap is normally in a discharged state. When the input transistor switches on, the left and right ends of the cap are pulled down and so is pin 2, triggering the 556. The cap quickly charges via the pull-up resistor on trigger pin 2, so pin 2 goes high again no matter how long the transistor stays on. When the transistor turns off, the cap discharges via the collector resistor and pull-up resistor.

Thanks for the explanation. That is a good idea. However, my design does work if I put a pull down resistor on the clock input of the 7474. As I was testing the circuit the clock input was floating, which the flip flop apparently doesn't like. Anyway, thanks for all the great answers. I have some ideas for a simpler design if this type of thing is ever needed again.