J-K Flip flop , initial state supposition ?

Discussion in 'General Electronics Chat' started by Xufyan, May 8, 2011.

  1. Xufyan

    Thread Starter Member

    Aug 3, 2010
    According to the table,

    J=0 , k=1 = RESET
    J=1 , k=0 = SET

    but see this JK Flip flop,
    initially when i suppose Q=0 (Reset), J=0 and K=1 and apply the first clock pulse then there are three input in gate 1,

    Q(bar) =1 , J=0 and Clock =1 this will make the the output of Gate 1 equals to '0' and the output of gate three become '1' (because Qbar is 1)

    but this is a wrong state :confused: Q must be equal to 0 when 'J' and 'K' equals to '0' and '1' respectively.


    I am just confused what should be the initial supposition for the J and K. ?

    any advice ?
  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
    When J=0, the output of gate 1 will always be 1.