Cyclic redundancy check codes (Design)

Discussion in 'Homework Help' started by afrina_21, Jun 5, 2016.

  1. afrina_21

    Thread Starter New Member

    Jun 5, 2016
    help me to understand this because i'm not allowed to use XOR gate to design the CRC generator

    Design, build and Test an 8-bit CRC generator. You should test your CRC generator by giving an input file of [11, AA, AC, DA, 59, A8, 9C, EF] or [00010001, 10101010,…… 11101111] to generate the checksum. Once you obtain the remainder (checksum), re-input the data along with checksum to your CRC generator to obtain 00H. This will confirm that your design is correct.

    • Your CRC generator must posses an accumulator to perform the division
    • Your design should input a 8-bit parallel data and NOT a serial data stream, thus DO NOT use an XOR gate (Different from most of the implementation found in the Internet)
    • You must input the generator using 8-bit at a time

    Show all your design step and use minimal gate for VHDL implementation or minimal cost for gate level implementation.
  2. WBahn


    Mar 31, 2012
    YOU need to show YOUR best attempt to at least start YOUR homework problem. That gives us a starting point from which to help guide you.

    Are you give a polynomial you are supposed to use, or do you get to choose it?

    Do you understand what an 8-bit CRC is?
  3. afrina_21

    Thread Starter New Member

    Jun 5, 2016
    we get to choose the polynomial
    yes, i do understand the 8-bit CRC which have 9 bits for its encoding

    what i want to do first is to use parallel-in and serial-out shift register to input 8-bit in parallel.then use another shift register to move the bits to left and use the accumulator to do the division. is it the right way to do it?