help me to understand this because i'm not allowed to use XOR gate to design the CRC generator
Design, build and Test an 8-bit CRC generator. You should test your CRC generator by giving an input file of [11, AA, AC, DA, 59, A8, 9C, EF] or [00010001, 10101010,…… 11101111] to generate the checksum. Once you obtain the remainder (checksum), re-input the data along with checksum to your CRC generator to obtain 00H. This will confirm that your design is correct.
Show all your design step and use minimal gate for VHDL implementation or minimal cost for gate level implementation.
Design, build and Test an 8-bit CRC generator. You should test your CRC generator by giving an input file of [11, AA, AC, DA, 59, A8, 9C, EF] or [00010001, 10101010,…… 11101111] to generate the checksum. Once you obtain the remainder (checksum), re-input the data along with checksum to your CRC generator to obtain 00H. This will confirm that your design is correct.
- Your CRC generator must posses an accumulator to perform the division
- Your design should input a 8-bit parallel data and NOT a serial data stream, thus DO NOT use an XOR gate (Different from most of the implementation found in the Internet)
- You must input the generator using 8-bit at a time
Show all your design step and use minimal gate for VHDL implementation or minimal cost for gate level implementation.