Hi everyone, I’m working on a project and I’m running into an issue where my FSM appears to be stuck in the OFF state and none of the outputs change in simulation. I’m using Quartus and implementing the state machine in a BDF schematic using 7474 flip-flops. I’ve attached my BDF schematic and VWF simulation file.

The assignment is to design a simplified adaptive cruise control system. We're told to assume the car cannot exceed 63 mph and that cruise can be enabled anywhere between 0–50 mph. The FSM must handle four situations:

1. OFF – cruise disabled
2. AUTO – cruise active and system automatically accelerates or decelerates based on LT/GT comparator inputs
3. DR – driver has pressed the accelerator; cruise stays active but system stops auto-control
4. BRK – brake pressed; cruise turns off and stays here until brake is released

Inputs:

• EN – enable cruise
• BR – brake
• ACC – accelerator
• LT – current_speed < set_speed
• GT – current_speed > set_speed

Outputs:

• CRU – cruise active
• ACCL – accelerate command
• DECL – decelerate command

State Encoding
I’m using two flip-flops (Q1, Q0):

State	Q1 Q0
OFF	00
AUTO	01
DR	10
BRK	11

FSM Behavior

• OFF → AUTO when EN=1 and BR=0
• AUTO → DR when ACC=1
• AUTO → BRK when BR=1
• DR → AUTO when ACC goes back to 0
• DR → BRK when BR=1
• BRK → stay BRK while BR=1
• BRK → OFF when BR returns to 0

LT/GT affect only the outputs (ACCL/DECL) in the AUTO state.

In VWF simulation, even after forcing Q1/Q0 to 0 at time 0 and toggling the inputs (EN, BR, ACC, LT, GT), the state bits never change and none of the outputs respond. Everything stays at OFF (00). CRU, ACCL, DECL all stay LOW through the entire simulation.

I verified:

• Clock is toggling cleanly
• PRE and CLR on the 7474s are tied high (VCC)
• Input nodes appear in the VWF
• Q1/Q0 appear in the waveform but don’t change
• Outputs are wired to observable pins

I suspect something is wrong with my next-state logic for D0 or possibly the way I implemented the OFF→AUTOtransition, since that’s the first required movement and it never happens. I also implemented state decoders (S_AUTO, S_DR, S_BRK) but I’m not 100% sure the wiring is correct.

If anyone could look at my attached files and help me figure out where I'm going wrong, that would be great

• Q1/Q0 never leave 00
• The FSM never reaches AUTO even when EN=1 and BR=0
• Outputs never respond

Thanks in advance for any help!

 

The 7474 outputs should be Q1/Q0 instead of Q2/Q1.