Hey all,
I have a digital design homework problem and I'm really foggy on how to construct a certain gate function. The problem is:
(a) Design the 8-input NAND gate using 2-input NAND gates and NOT gates.
(b) Design the 8-input NAND gate using 2-input NAND gates, 2-input NOr gates, and NOT gates if needed?
I forgot how to construct these buggers. Can anyone point me in the right direction?
I have a digital design homework problem and I'm really foggy on how to construct a certain gate function. The problem is:
(a) Design the 8-input NAND gate using 2-input NAND gates and NOT gates.
(b) Design the 8-input NAND gate using 2-input NAND gates, 2-input NOr gates, and NOT gates if needed?
I forgot how to construct these buggers. Can anyone point me in the right direction?