# Conditional Makefile

#### sakitten123

Joined Dec 9, 2015
1
I have an embedded project that needs to run on two different flash memory sizes of the microcontroller family. All code is written in C.

The code is exactly the same except:
- a few #defines in a header file
- a few variable values in a function in a source file

I feels unnecessary to have two separate branches in source control, two places to do bug fixes, two FW versions to test and validate before product release etc. Especially since the differences are so small..?

What I would like is to have two versions of the header file in question and two versions of the source file in question. And then have some condition in the Makefile to compile one of the two. Sounds reasonable?

Something like this:
Code:
Makefile
ifeq (condition)
C_OBJECTS += SourceFile1.o
endif
ifeq (condition)
C_OBJECTS += SourceFile2.o
endif
And SourceFile1 and 2 respectively include header file 1 and 2 as:
Code:
SourceFile1.c
//code
and
Code:
SourceFile2.c
//code
The problem is that HeaderFile1.h is included in quite a lot of the other source files in the project. I guess their includes would have to change to HeaderFile2.h based on the Makefile condition. That seems a bit harder to accomplish. With my above reasoning it would mean having to have two different versions of all source files that includes that paricular header file and compile one of the two based on the condition. That's not what I'm after.

Do I want to do something that is not possible? Do you have any other ideas of how to solve this?

Any help would be greatly appreciated!

#### MrChips

Joined Oct 2, 2009
22,577
Use conditional compilation.
Use one makefile, one header file and one set of source files.

#define LARGE_MEMORY_MODEL

In your source code, use conditional compilation:

#ifdef LARGE_MEMORY_MODEL

// code for large memory here

#else

// code for small memory here

#endif