For our application, the lowest frequency of interest is as close to 0Hz (DC) as possible, the highest frequency of interest ranging between 100-120 Hz.What is you signal's lowest frequency of interest?
For our application, the lowest frequency of interest is as close to 0Hz (DC) as possible, the highest frequency of interest ranging between 100-120 Hz.What is you signal's lowest frequency of interest?
Of all the models of practical op-amps I have seen till date, the input bias current is modelled as a current source to the inputs, directly into the ground, bypassing the op-amp's input impedance. I don't understand that very well.For some kinds of calculations these impedances are relevant; but I've never needed to consider them when doing noise analyses.
Because the noise current flows independent of the amplifier input impedance (looks like a current-source).the input bias current is modelled as a current source to the inputs, directly into the ground, bypassing the op-amp's input impedance. I don't understand that very well.
Not an accurate interpretation.The input bias currents should be flowing between each of the inputs and ground, through the respective (matched) common-mode input impedance of each input, and the input offset current should be flowing between the two inputs only through the differential-mode impedance.
Is that so?
No. What @crutschow wrote above is correct and complete.The input bias currents should be flowing between each of the inputs and ground, through the respective (matched) common-mode input impedance of each input, and the input offset current should be flowing between the two inputs only through the differential-mode impedance.
Is that so?
Yes, of course.It's the noise current flowing through the external input impedance that causes a noise voltage, not it flowing through the amplifier internal input impedance.
Yes, I agree with that too.The input bias current flows equally from the the two inputs through the external circuit impedance at the input nodes.
The input offset current is the difference between the two input currents.
The "input impedance" is not a discrete resistance at the input to the op amp as you seem to think.I would be really grateful if someone could point out where I am going wrong, so that I might clear my misconceptions.
The input bias current and input offset current appear in parallel with the common-mode and differential-mode input impedances, not in series with them. I think that's where the misconception lies.I would be really grateful if someone could point out where I am going wrong, so that I might clear my misconceptions.
Consider what that would mean in the case of an OP177G, if it were so: the part has a maximum input bias current of 2.8 nA and a common-mode input impedance of 200 GΩ, and this would create a voltage drop of 560 volts if the input bias current were flowing through it. Obviously impossible.we can model the input bias currents as equal current flowing between each of the inputs and the ground, through the common-mode impedance, inside the op-amp.
Consider what that would mean in the case of an OP177G, if it were so: the part has a maximum input bias current of 2.8 nA and a common-mode input impedance of 200 GΩ, and this would create a voltage drop of 560 volts if the input bias current were flowing through it. Obviously impossible.
Yes, right!The input bias current and input offset current appear in parallel with the common-mode and differential-mode input impedances, not in series with them. I think that's where the misconception lies.