# Comparing noise specs in precision Op-Amps

#### Abbas_BrainAlive

Joined Feb 21, 2018
113
What is you signal's lowest frequency of interest?
For our application, the lowest frequency of interest is as close to 0Hz (DC) as possible, the highest frequency of interest ranging between 100-120 Hz.

#### Abbas_BrainAlive

Joined Feb 21, 2018
113
For some kinds of calculations these impedances are relevant; but I've never needed to consider them when doing noise analyses.
Of all the models of practical op-amps I have seen till date, the input bias current is modelled as a current source to the inputs, directly into the ground, bypassing the op-amp's input impedance. I don't understand that very well.

The input bias currents should be flowing between each of the inputs and ground, through the respective (matched) common-mode input impedance of each input, and the input offset current should be flowing between the two inputs only through the differential-mode impedance.

Is that so?

#### crutschow

Joined Mar 14, 2008
26,814
the input bias current is modelled as a current source to the inputs, directly into the ground, bypassing the op-amp's input impedance. I don't understand that very well.
Because the noise current flows independent of the amplifier input impedance (looks like a current-source).
It's generally caused by the bias current required by the input transistors.
The input bias currents should be flowing between each of the inputs and ground, through the respective (matched) common-mode input impedance of each input, and the input offset current should be flowing between the two inputs only through the differential-mode impedance.
Is that so?
Not an accurate interpretation.
The input bias current flows equally from the the two inputs through the external circuit impedance at the input nodes.
The input offset current is the difference between the two input currents.

Neither have anything to do with the amplifier input common-mode or differential-mode impedance.

It's the noise current flowing through the external input impedance that causes a noise voltage, not it flowing through the amplifier internal input impedance.

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#### OBW0549

Joined Mar 2, 2015
3,566
The input bias currents should be flowing between each of the inputs and ground, through the respective (matched) common-mode input impedance of each input, and the input offset current should be flowing between the two inputs only through the differential-mode impedance.

Is that so?
No. What @crutschow wrote above is correct and complete.

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#### Abbas_BrainAlive

Joined Feb 21, 2018
113
It's the noise current flowing through the external input impedance that causes a noise voltage, not it flowing through the amplifier internal input impedance.
Yes, of course.

The input bias current flows equally from the the two inputs through the external circuit impedance at the input nodes.
The input offset current is the difference between the two input currents.
Yes, I agree with that too.

But what happens when the input bias current enters the op-amp? It cannot simply disappear! It has to flow to the point of zero potential (the system ground), and so it is modelled as a current source between the inputs and the ground. So, there has to be a conduction path. And, the only conduction path I am aware of, inside an op-amp, is the input impedance. So, if the input bias currents are flowing to the ground, they either have to flow through the internal common-mode impedance, or there is another zero-impedance path between the inputs and the ground, inside the op-amp.

This is how I interpret input offset current as well. Input bias currents are ideally equal in both the inputs. But, since, due to manufacturing tolerances, the input bias currents are not the same, and the difference between the input bias currents is called the input offset current, we can model the input bias currents as equal current flowing between each of the inputs and the ground, through the common-mode impedance, inside the op-amp. And the difference between both the input bias currents, as seen by the external circuitry, makes up for the input offset current flowing between the inputs. And this flow of input offset current can only be through the differential-mode input impedance, since there is no other conduction path present between the inputs, inside the op-amp.

I know this is not the generally accepted concept of input bias currents, input offset current, and the input impedances. But this is how it comes to me when I consider the basics of electricity.

I would be really grateful if someone could point out where I am going wrong, so that I might clear my misconceptions.

#### crutschow

Joined Mar 14, 2008
26,814
I would be really grateful if someone could point out where I am going wrong, so that I might clear my misconceptions.
The "input impedance" is not a discrete resistance at the input to the op amp as you seem to think.
It is the impedance of the input transistors in the op amp input amplifier stage.

And the "input bias current" is the input base current of these transistors.
Of course from there it then flows to the power supply rails as part of the transistor current.

So the bias current does not "flow through" the input impedance, it is an intrinsic part of the circuit the provides this "input impedance".

You appear to be overthinking the whole thing.

#### Abbas_BrainAlive

Joined Feb 21, 2018
113

#### OBW0549

Joined Mar 2, 2015
3,566
I would be really grateful if someone could point out where I am going wrong, so that I might clear my misconceptions.
The input bias current and input offset current appear in parallel with the common-mode and differential-mode input impedances, not in series with them. I think that's where the misconception lies.

we can model the input bias currents as equal current flowing between each of the inputs and the ground, through the common-mode impedance, inside the op-amp.
Consider what that would mean in the case of an OP177G, if it were so: the part has a maximum input bias current of 2.8 nA and a common-mode input impedance of 200 GΩ, and this would create a voltage drop of 560 volts if the input bias current were flowing through it. Obviously impossible.

#### Abbas_BrainAlive

Joined Feb 21, 2018
113
Consider what that would mean in the case of an OP177G, if it were so: the part has a maximum input bias current of 2.8 nA and a common-mode input impedance of 200 GΩ, and this would create a voltage drop of 560 volts if the input bias current were flowing through it. Obviously impossible.

The input bias current and input offset current appear in parallel with the common-mode and differential-mode input impedances, not in series with them. I think that's where the misconception lies.
Yes, right!

Thanks a lot,

#### Analog Ground

Joined Apr 24, 2019
448
Summing noise sources and doing trade offs is tedious and complex if done by hand. I suggest modeling with LTspice or another Spice simulator which has noise analysis. Not perfect but a good place to start. Many models from major manufacturers do a good job of modeling noise with one exception which is 1/f noise. The Analog Devices and LTspice combination is a good place to start.