Comparator symbol

Thread Starter

anhnha

Joined Apr 19, 2012
880
I am a bit confused about the symbol of comparator in the picture below. As you can see, there is a circle after the comparator. Does it mean a NOT gate here?

Maximum power point tracking.png
 

Thread Starter

anhnha

Joined Apr 19, 2012
880
Thanks. I also thought like that but the circuit description doesn't seem to be matched with the symbol here. For the description to be right, the circle symbol should not be there at all.
Circuit Description.png
 

sailorjoe

Joined Jun 4, 2013
361
OK, so let's think this through. The osc is putting out a sawtooth wave that ramps from zero to some maximum. That's on the negative input. The positive input has some value that is around 1/2 Vsrc, depending on exactly when the S&H picked up the sample, and on what is happening dynamically. Let's just assume for the moment that the value into the second comparator is a fixed value.

As the ramp starts at it's lowest value the output of a normal comparator would be High, because V+>V-. But for this one it's Low. Q1 is off, and the Mp is conducting. As the ramp increases, it eventually get's higher than V+ and the comparator switches from Low to High, which turns on Q1 and turns off Mp.

If V+ goes up on the next sample, then Q1 will stay off longer, Mp will conduct longer which is the same as increasing the duty cycle D. Doesn't that match the description in the attachment?
 

Thread Starter

anhnha

Joined Apr 19, 2012
880
I don't quite understand what you said. For the first comparator assuming that Vsrc is larger than Vh, its output is high resulting output of the second comparator is a pulse with D increases or big => The voltage at collector of Q1 will have D small. This is opposite with what is said in the description above.
 

Thread Starter

anhnha

Joined Apr 19, 2012
880
Here is what I understand the circuit:
Vref is the output of the first comparator. If Vref is large then duty cycle D is small and vice versa.
Now with the circuit above, if Vsrc is larger than Vh then the output of the first comparator is HIGH. This means that the pulse at the output of the second comparator without NOT will have small D. And the pulse after the NOT will have large D.
Q1 acts as an inverter here. So the pulse at the collector of Q1 will have small D. That doesn't match with the circuit description above.
What is wrong here?


saw - pwm.PNG
 
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