Hi!
A am newbie with VHDL code programming for FPGA and I need some help.
I have simulation described on the blackboard. Here are described two variants:
Is it possible to write a code to FPGA based only on this?
Could you tell me as simple as it possible how to make it?
Co przedstawiają rozrysowane dwa warianty?
What does two variants show? (is it counter, register, ...?)
Czy w każdym wariancie są po 3 czy 4 sygnały? (do czego jest podłączony sygnał DATA?)
Does in each variants there are 3 or 4 signals? (what does DATA signal connected to?)
I work with Nexys™3 Spartan-6 FPGA Board.
Sorry if I wrote it in a wrong place but, it is very important for me.
Thank for reply!
A am newbie with VHDL code programming for FPGA and I need some help.
I have simulation described on the blackboard. Here are described two variants:
Is it possible to write a code to FPGA based only on this?
Could you tell me as simple as it possible how to make it?
Co przedstawiają rozrysowane dwa warianty?
What does two variants show? (is it counter, register, ...?)
Czy w każdym wariancie są po 3 czy 4 sygnały? (do czego jest podłączony sygnał DATA?)
Does in each variants there are 3 or 4 signals? (what does DATA signal connected to?)
I work with Nexys™3 Spartan-6 FPGA Board.
Sorry if I wrote it in a wrong place but, it is very important for me.
Thank for reply!