From alpha power law,analytical delay model for CMOS inverter is given by

DELAY directly proportional to VDD/(VDD-VTh)^alpha

Using this equation how do i calculate the delay for inverter and what should be the proportionality constant..i have extracted Vthn=0.6 ,Kn=0.0007 alphan=1.5, Kp=0.00049 Vthp=0.5 , alphap=1.1 from MATLAB curve fitting and VDD varies from 0.2V - 0.4V..I m using 16nm LP model file from ASU...output load capacitance is 1aF.. But since Vth is greater then VDD it returns complex values for delay..

 

Hi,

All i can offer here is that when you use an equation that yields a complex value the way you handle it depends on the physical problem at hand and that comes from the theory behind it, and that can vary from one type of problem to another. For example sometimes you take the real part, sometimes the imaginary part, and sometimes the complex absolute value, but still yet other times it means an error in one the parameter values.

I would have to ask here though how does Vdd get to be so low. Is that the power supply voltage?

I had some equations for CMOS many years back but cant seem to find them now. I thought they were in a CMOS book i had but i checked and cant find them. I know i posted them on some site like this some years ago, but not sure which one now.

 

Hi,

All i can offer here is that when you use an equation that yields a complex value the way you handle it depends on the physical problem at hand and that comes from the theory behind it, and that can vary from one type of problem to another. For example sometimes you take the real part, sometimes the imaginary part, and sometimes the complex absolute value, but still yet other times it means an error in one the parameter values.

I would have to ask here though how does Vdd get to be so low. Is that the power supply voltage?

I had some equations for CMOS many years back but cant seem to find them now. I thought they were in a CMOS book i had but i checked and cant find them. I know i posted them on some site like this some years ago, but not sure which one now.

yes its power supply voltage..since its LP model(low power)max supply voltage is 0.9

 

yes its power supply voltage..since its LP model(low power)max supply voltage is 0.9

Hi,

Well then how did you come to the conclusion that Vdd had to range from 0.2 to 0.4v.
It looks like one possibility is that Vdd must always be greater than Vth, and that sounds more realistic because if it is CMOS then you can not turn it on in a reasonable way without the proper supply voltage.

But unfortunately you are not giving enough information to be sure about any of this. Can you perhaps link to a site with more information about what you are talking about? That would help a lot i think.

 

Hi,

Well then how did you come to the conclusion that Vdd had to range from 0.2 to 0.4v.
It looks like one possibility is that Vdd must always be greater than Vth, and that sounds more realistic because if it is CMOS then you can not turn it on in a reasonable way without the proper supply voltage.

But unfortunately you are not giving enough information to be sure about any of this. Can you perhaps link to a site with more information about what you are talking about? That would help a lot i think.

I m trying to implement a paper..I have attached the reference paper..

 

Hello again,

Another question, is this model considered valid for Vdd<Vth ?
Is it possible that you are to use alpha equal to 1 or 2 ?

If not, then if we assume that Vth>Vdd then we have the following identity:
Vdd/(Vdd-Vth)^a=cos(pi*a)*Vdd/(Vth-Vdd)^a-i*sin(pi*a)*Vdd/(Vth-Vdd)^a

and this admits to having an imaginary part for some values of 'a' like a=1.3 for example.

If you want to understand the model you are using better you have to find a paper on that model, not on some new model that only mentions the model you are using in passing. That's the best way.