Circuit Analysis: OP Amp Problem

Thread Starter

WilkinsMicawber

Joined Jun 5, 2017
29
I am having trouble with 2 fairly straightforward problems.

In the first, I am attempting to analyze the following:
hw 1.jpg
Capacitors are treated as open circuits in DC. With this assumption, nodal analysis yields the following: Vo = 2 * V1, and Vo = 2 * V1 - Vi. These 2 equations seem to be contradictory, and i'm not sure how to resolve the contradiction.

In the last problem, shown below, I think I have the solution, but my simulation of it in multisim gives unexpected results:
hw 2.jpg
Through nodal analysis I get io = 20,000is, but in multisim the behavior of the output is unpredictable. Is that not the right interpretation of the above circuit? Here is my multisim version of it, in case any of you might be able to see where I erred:
hw 3.jpg
 

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WBahn

Joined Mar 31, 2012
32,823
If the assumption that the voltages at the two inputs of an opamp are the same leads to a contradiction, then the most reasonable conclusion is that the assumption is not valid.

So reanalyze the circuit without making that assumption.
 

Thread Starter

WilkinsMicawber

Joined Jun 5, 2017
29
I'm not really sure what the purpose of the 2nd circuit is, although I have two equations relating four variables that reflect what's happening in multisim.
 

RBR1317

Joined Nov 13, 2010
715
To get something meaningful you need to solve for V1 & V2 in terms of Vi & Vo -- rearranging your equations gives:

V1 = ½(Vo+Vi)
V2 = ½Vo

So if Vi is just +1 microvolt, then V1 will be greater than V2 and Vo will saturate at the highest positive value. What happens if you account for the presence of C?
 

MrAl

Joined Jun 17, 2014
13,702
I am having trouble with 2 fairly straightforward problems.

In the first, I am attempting to analyze the following:
View attachment 134608
Capacitors are treated as open circuits in DC. With this assumption, nodal analysis yields the following: Vo = 2 * V1, and Vo = 2 * V1 - Vi. These 2 equations seem to be contradictory, and i'm not sure how to resolve the contradiction.

In the last problem, shown below, I think I have the solution, but my simulation of it in multisim gives unexpected results:
View attachment 134609
Through nodal analysis I get io = 20,000is, but in multisim the behavior of the output is unpredictable. Is that not the right interpretation of the above circuit? Here is my multisim version of it, in case any of you might be able to see where I erred:
View attachment 134615
Hello there,

What aer you trying to accomplish with this circuit, that is, what are you trying to find out?
You seem to have two different configurations later on, why do that, what is the goal here?

It is true that for DC we *usually* open circuit the capacitors, but in real life when the circuit first starts up the capacitor will take some time to reach some equilibrium state and so if we eliminate the capacitor we could miss the expression that tells us how this works.
By analyzing the circuit with the capacitor intact, we get to see how the output changes as the circuit starts up, and that could provide valuable information about what we can expect from this circuit.
In particular, we might get an expression like this:
Vout=A-B*e^(-t/C)

or like this:
Vout=A-B*e^(t/C)

and we can see that with the first expression it looks stable, but with the second expression it looks like it goes into a saturation state after some time passes.

Also, if you want to understand both circuits then one way to do that would be to analyze BOTH circuits at the same time, then change things later. This results in one equation with some variables. This involves keeping both the current source and the input voltage source in the circuit, then later zeroing one out.
For example, with all resistors the same value equal to R1 (one of your circuits) we might get this for a step input of both:
Vout=(2*t*E1)/(C1*R1)-(2*t*I1)/C1-I1*R1

and we can see that we have two ramps, one caused by the current source I1 and one caused by the input voltage source E1, and the current source leads to a negative ramp and an offset, and the voltage source leads to a positive ramp with no offset but there is no end to the rise. This means either form saturates the output with a step input.

So you can try keeping the capacitor in the circuit and that should help you get a better grasp of what is going on with this circuit for either input type and various value resistors.
 
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