Hello all!

I am facing some challenges in designing a 4th order Butterworth LPF, implemented in MFB architecture. Since the LPF is of 4th order, it is divided into two stages cascaded together, each stage comprising of a second order Butterworth LPF. The schematic for each of the stage (2nd order Butterworth) and its transfer function is depicted in the following image.


The filter parameters can be mathematically represented through the following equations.


The optimised values for these filter characteristics have been documented in the following table.


For my application, I chose the gain of each stage to be 10x, and the cut-off frequency to be about 1KHz. The component values I am using for each of the stages are mentioned below.

Stage 1:
R1 (E) = 150
R2 (E) = 1500
R3 (E) = 5600
C1 (nF) = 4.7
C2 (nF) = 680
K = -10
FSF*fc = 971.3530391
FSF=1
fc (Hz) = 971.3530391
Q = 0.552479046

Stage 2:
R1 (E) = 680
R2 (E) = 6800
R3 (E) = 10000
C1 (nF) = 1
C2 (nF) = 330
K = -10
FSF*fc = 1062.4505
FSF=1
fc (Hz) = 1062.4505
Q = 1.282533103

The filter is working fine, but with three major problems.
1. The output response should show a gain of 10x, but it is neither showing any gain nor attenuation.
2. A glitch/spike is observed near each zero-crossing, its magnitude is very small at the output of the first stage but very large at the output of the second stage. Please find the snapshots of the input sine wave and outputs of both the stages in the attachments.
3. The system gives a cut-off frequency of about 160Hz (far less than the calculated value).

The magnitude of these glitches/spikes increase exponentially with frequency, and it is clearly evident especially in the output of the second stage.

As for the physical implementation of the system, it has been implemented on a PCB with SMD components, resistors having a tolerance of 1% and capacitors that of 5%.

I have tried different implementations by modifying the values of the discrete components as well as using a different Op-Amp IC, the results are more or less the same.


I would be really grateful if someone could point out what I am doing wrong.

Best regards,
Abbas.

 

The lack of any gain difference between input and output and the fact that the rolloff frequency is the same as the RC at the input of each two pole block points strongly to non-functioning opamps.

What opamp are you using and what power supplies are you using?

Wildly extrapolating from a thin filament of information, my first guess would be that you are running on a single positive power supply and that would likely be the problem.

 

and the fact that the rolloff frequency is the same as the RC at the input of each two pole block points strongly to non-functioining opamps.

Simply WOW!

I didn't look at it that way!

And, you are perfectly right! I confirmed it practically, by tieing the reference line of the filter circuit to the midpoint of the power supply.

Thank you very much.

But then, I am now facing an even bigger challenge.

The filter needs to operate on the output of an IFDIA, whose reference is tied to the mid-point of the power supply and the reference line of the filter is the inverting output of the IFDIA. So, I cannot tie both the reference as well as the inverting output of the IFDIA to the mid-point of the power supply (virtual ground).

What should I do?

Also, you clearly mentioned the reason behind no gain and the low cut-off frequency, but I still cannot understand the reason behind the glitch/spike. It would be really appreciable if you could describe a bit more about it.


Thanking you once again, and awaiting your response,
With best regards,
Abbas.

 

It was only because of your unusually complete description of the problem that it would be diagnosed so quickly.

Without know for sure what an IFDIA is I will continue. Would you please describe the IFDIA -especially the output signal level and the impedance? Also what is the quiescent output voltage (when there is no excitation)?

If the power supply midpoint is not buffered, then adding a buffer to the output would probably prevent any undesired cross talk between the (virtual) ground currents from the filter stages (those from both occurrences of C2) and the reference input of the IFDIA.

Can the circuit that your filter is driving operating with the filter's output referenced to half the power supply level, or would it be better to make a negative power supply?

One guess is that the glitch was the result of the input voltage swinging far enough from its V- terminal for the opamp to operate with only a positive power supply. Many opamps cannot operate with their opamps at or below the negative power supply pin and many cannot swing their outputs all the way to the power supply rails, so the glitch was the opamp suddenly starting to work.

 

Would you please describe the IFDIA

Integrated, Fully-Differential Instrumentation-Amplifier.

If the power supply midpoint is not buffered, then adding a buffer to the output would probably prevent any undesired cross talk between the (virtual) ground currents from the filter stages (those from both occurrences of C2) and the reference input of the IFDIA.

I don't think this would work, as the reference and the output(s) are electrically connected in an In-Amp.

Can the circuit that your filter is driving operating with the filter's output referenced to half the power supply level, or would it be better to make a negative power supply?

I suppose both are the same things, electrical/electronic machines/devices work due to the electrical potential of one point with respect to the other point, positive and negative are just symbols to ease our understanding of things. The ground is the negative supply for the mid-point, isn't it so?

One guess is that the glitch was the result of the input voltage swinging far enough from its V- terminal for the opamp to operate with only a positive power supply. Many opamps cannot operate with their opamps at or below the negative power supply pin and many cannot swing their outputs all the way to the power supply rails, so the glitch was the opamp suddenly starting to work.

If that would have been the case, we should have observed a chopped or clamped output, but there is no chopping or clamping, but just a single, repeated glitch/spike.

With best regards,
Abbas.

 

I am not getting the "picture". Would you please post the instrumentation amplifier circuit and describe its input signal.

To what does does the output of the filter connect? Does the output need to be around ground or can it be floating at another voltage?

 

The following block diagram might give you a better idea.



The 4th order filter needs to act on these outputs of the IFDIA, namely OUTA+ and OUTA-, and the output of the filter is fed into a differential-input ADC. In this case, the filter acts on differential lines and does not have a reference pin/line, while the IFDIA, as well as the (differential-input) ADC, are referenced about the (virtual) ground, midway between the power supply lines.

Please note that the differential lines means that they would have the exact magnitude with respect to the (virtual) ground, but in opposite polarity, this helps in minimizing CM (common-mode) noise, and thus, enhancing the system's noise immunity.

Moreover, I am still not able to figure out the reason behind that glitch!

With best regards,
Abbas.

 

From your latest post I believe that everything can be referenced to the supply's mid-point. Since you did not mention the nature of the input signal I will assume that you are ok with letting the instrumentation amplifier handle any offset that might appear to be present at the input as a result of using the supply midpoint for a reference rather than ground.

After moving the circuit's reference to the supply midpoint is the glitch still there? If the glitch is still there, then perhaps trying a faster opamp will solve the problem. What opamps are you using and how many volts is the power supply?

 

From your latest post I believe that everything can be referenced to the supply's mid-point.

Yes, that's exactly why I mentioned it to be virtual ground. Effectively, a unipolar battery acts as a bipolar supply, the midpoint being the (virtual) ground for the system.

Since you did not mention the nature of the input signal

The input is a bipolar signal.

I will assume that you are ok with letting the instrumentation amplifier handle any offset that might appear to be present at the input as a result of using the supply midpoint for a reference rather than ground.

I suppose, this question is already answered in my first statement in the current post.

After moving the circuit's reference to the supply midpoint is the glitch still there?

No, it isn't. Now the output is perfectly smooth, with the expected gains at the output of each of the two stages.

But, as you suggested,

One guess is that the glitch was the result of the input voltage swinging far enough from its V- terminal for the opamp to operate with only a positive power supply. Many opamps cannot operate with their opamps at or below the negative power supply pin and many cannot swing their outputs all the way to the power supply rails, so the glitch was the opamp suddenly starting to work.

If that would have been the case, we should have observed a chopped or clamped output, but there is no chopping or clamping, but just a single, repeated glitch/spike.

 

Maybe, but when the input voltage exceeds the input voltage limits of the opamp all bets are off and strange things including the wildly popular feature: signal inversion can take place.

I'm glad to hear that the glitch is no longer a problem.

 

I'm glad to hear that the glitch is no longer a problem.

All thanks to your guidance.
I am truly grateful.

But my problem about how to handle the differential signals from the IFDIA, through the filter, and into the (differential-input) ADC is still unresolved. Would you like to suggest something else?

Thanking you once again,
With best regards,
Abbas.

 

What part is unresolved?

(I will be away for several hours this time.)

 

1) What is the resolution of the ADC you are going to use ?

2) What is the range of of signals going into the IFDIA ? Both CM
and pk-pk ?

3) What are you doing with the ADC output ?

4) Do you need to filter differentially the output of the IFDIA or can you just
handle it as single ended ?


Regards, Dana.

 

Do you need to filter differentially the output of the IFDIA or can you just
handle it as single ended ?

Yes, this is the part that is left unresolved. And yes, I need to filter the signal differentially, single-ended filtering won't just do!


Does the ADC resolution and what is being done with the ADC output hold any significance here?

The IFDIA inputs are well within the acceptable range, none of the amplifiers is experiencing any kind of saturation.

The challenge is how to make the filter work properly!

The 4th order filter needs to act on these outputs of the IFDIA, namely OUTA+ and OUTA-, and the output of the filter is fed into a differential-input ADC. In this case, the filter acts on differential lines and does not have a reference pin/line, while the IFDIA, as well as the (differential-input) ADC, are referenced about the (virtual) ground, midway between the power supply lines.

The filter works only when its reference line is tied to the (virtual) ground, but the application does not allow it, as the reference line of the filter is the inverting output of the IFDIA.

With best regards,
Abbas.

 

The reason I asked the questions is a possible single chip solution IA, ADC,
reference, UP, filter (digital filter)....... for future design consideration.

Regards, Dana.

 

(Some text removed for clarity)

The filter works only when its reference line is tied to the (virtual) ground, but the application does not allow it, as the reference line of the filter is the inverting output of the IFDIA.

With best regards,
Abbas.

It took some time for this to sink in. Every time I read [the above] I understood it as the virtual ground being the inverting input of the IFDIA because using the output did not make any sense. It still does not.

If you can post a schematic showing how the elements of your circuit are interconnected we can probably get to a good solution quickly.

 

Here's a paper on differential MFB active filters that may be of interest.

 

Here's a paper on differential MFB active filters that may be of interest.

I really appreciate your willingness to help, crutschow, but the link seems to be pointing to the local address of the pdf file you are trying to share. Please share the pdf directly as an attachment in this thread, or upload it on a file hosting platform and share the download link.

If you can post a schematic showing how the elements of your circuit are interconnected we can probably get to a good solution quickly.

Here is an approximate schematic.


U1.1 is the IFDIA and U4, along with all the discrete components, comprise the 4th order Butterworth filter, in MFB architecture.
J2 (U1.1:1 and U1.1:2) is for IFDIA gain selection.
U1.1:4 and U1.1:5 are the non-inverting and inverting inputs of the IFDIA.
U1.1:6 and U1.1:3 are the buffered outputs of non-inverting and inverting inputs of the IFDIA.
U1.1:11 is the IFDIA reference pin, tied to (virtual) GND (buffered midpoint between the power-supply rails).
J11 is for the amplified, filtered, differential output.

Thanks and regards,
Abbas.

 

Try this link for crutschow's file: www.ti.com/lit/an/slyt343/slyt343.pdf

It looks like it can lead you to a quick solution.

 

Try this link for crutschow's file: www.ti.com/lit/an/slyt343/slyt343.pdf

Wonderful article! Thanks a lot, DickCappels.