Value given:
R1 = 22K, R2 = 2.2K, R3 = 1.5K, R4 = 120oHm, RL = 1K, C1 = 1uF, HFE = 200

i just made the calculation for this amplifier, but i suspect that it is not correct so hope someone can verify for me
Sorry for the noob question

for DC bias,
Rin = R1||R2||(Hfe*R4) = 1846ohm
VBQ1 = (R2/(R1+R2)*24v)-12v = -9.8V
VE = -VBQ1 - 0.7 = -10.5
IE = (12V+(-VE))/R4 = 12.5mA
VB2 = +12V - IE* R3 = -6.75V
VB3 = VB2 - (3*VBE) = -8.85V
VE2 = VB2 - VBE = -7.45
VE3 = VB3 + VBE = -8.15

Peak output current is 12V/RL = 12mA
the voltage gain is Rc/R4, where Rc = R3||((B+1)(r'eQ3+RL) = 1489
so Rc/R4 = 12.4
for a 4Vpeak to peak input signal, a peak input current are 2V/Rin = 1.08mA
so the total current gain is Peak output current/(2V/Rin) = 11.1

there are also few question i wanna ask
1) how to calculate the IE and IC for Q2 and Q3?

2) is that correct for the calculation of Rc = R3||((B+1)(r'eQ3+RL)?

3) how to calculate the maximum input signal voltage(rms) that avoid distortion for frequency of 10kHz? I know we use AC and DC load line to calculate for CE stage, but what for the whole circuit? or i just simply calculate the CE stage?

 

Don't forget that Q1 has an internal emitter resistance (0.026 /IE) that is in series with R4 and it will reduce the voltage gain a little.

I simulated your circuit and found Q1 to be turned on too much and making the DC output voltage -5.9V instead of 0V. So the output clips with an input of only about 340mV peak.
I increased the value of R1 to 30k which made the DC output voltage 0V and the input was increased to 800mV peak without distortion.

 

Don't forget that Q1 has an internal emitter resistance (0.026 /IE) that is in series with R4 and it will reduce the voltage gain a little.

I simulated your circuit and found Q1 to be turned on too much and making the DC output voltage -5.9V instead of 0V. So the output clips with an input of only about 340mV peak.
I increased the value of R1 to 30k which made the DC output voltage 0V and the input was increased to 800mV peak without distortion.

thanks for performing simulation for me , now i m sure that my calculation was rite~

How about the calculation of maximum undistorted ic(max), undistorted vce, and undistorted output voltage (ic(max)*RC||RL)? can someone show me all the AC & DC load line calculation and the equation used?

and to calculate the critical low frequency of C1(my own circuit without modification of R1), i use 1/(2PI*Rin*C1), where Rin = R1||R2||(B+1)(r'e1+R4) and get the value of 86hz, it this correct? cause when i simulate with multisim, i only get output voltage drop when reach lower than 200hz. hope someone can verity for me

sorry for being too greedy for answer cause i am really sux at this

 

nobody can help me with the AC/DC load line and the maximum undistorted output voltage calculation?

 

You can draw a load line for Q1 if you want then reduce it by the 0.7V base-emitter voltage drop of Q2.

My simulation shows that the max undistorted output is a little less than 8V peak-to-peak (I added incorrectly before so 11.2V p-p is wrong) because the amplifier is biased wrong and its output voltage is too much negative. Its max undistorted output is 7V p-p.
Its voltage gain is 11.67.

C1 reduces the output by 3dB at 86.7Hz.

 

Please,before you get too lost in mathematical calculations-this amplifier is not a very good example of good design.In practice it will barely work. Most important change is that R1 should be connected to the output instead to give DC feedback.
Better still add another transistor in front and then you have a perfectly normal amplifier,although it will still be lacking several refinements that can be done.

 

The teacher gave the lousy amplifier as an example so we are analysing the lousy amplifier.

Have you ever bought a transistor that has an HFE of exactly 200 when you asked for it?