"CD4026 Questions" revisited (divide by 6)

Discussion in 'General Electronics Chat' started by cornishlad, Mar 26, 2015.

  1. cornishlad

    Thread Starter Member

    Jul 31, 2013
    Probably only clock builders will be interested in this ! I've read the above thread and think I've just about understood Bill Marsden's scheme for counting to 6 using a separate 4013 counter to generate the reset.
    However, I've been wondering if an inverted "carry out" is nand gated with the "e" led section might be viable. This signal being obtained by inserting an opto-isolator in series with the "e" led feed (with adjustment of the series resistor for that segment). Any issues with this idea ?
  2. Papabravo


    Feb 24, 2006
    A schematic would be helpful. It sounds like you want to use an opto for a purpose other than isolation. It sounds a bit goofy from the description and not something that would have occurred to me. You must be aware that most optos have a rather long delay time. Don't know if that would be a problem here. You also know that CTR degrades with age -- right?
  3. AnalogKid

    AAC Fanatic!

    Aug 1, 2013
    The e segment comes on for both 2 and 6.

  4. cornishlad

    Thread Starter Member

    Jul 31, 2013
    That's why it would need gating with the inverse of "carry out" which would go high at 5. I will try and do a drawing
  5. cornishlad

    Thread Starter Member

    Jul 31, 2013
    Ok..I've re-read the original thread and now seen this from http://home.btconnect.com/brettoliver1/masterclock.htm (the first diagram and the link is from the original thread)
    This designer has used the segment feeds directly as logic levels to detect the exclusive condition where, for the first time in a count b=off and e =on.
    I had thought that these led outputs can't be used as logic levels but maybe at very low working voltage (with no series resistors) it will work. So that's one possibility. ?
    I've used the same diagram to show the opto-coupler idea 4026 divides by 60 opto.jpg (modified in photoshop - no circuit drawing software here)
    I mentioned a NAND gate in my OP but here the "masterclock" diagram shows a NOR gate and I've stuck with that. Only one required.
    I've never used an opto coupler so am not sure about the input current requirement. Maplin advertise a "low current" one with no additional info, and the data sheets I've seen only give a max 50ma.
    However something around 10ma should work (I saw a graph somewhere). r1 in the attached diagram needs adjusting lower than the other segment r's.
    The logic is "carry out" goes low after count of 5. On the count of 6 "b" goes high and opto output also goes low. The NOR gate out puts a high and resets the counter.
    Because I'm not an electronics engineer, and like papabravo "above" am a retired senior citizen, I'm hoping others with more knowledge will comment on this unusual use of the opto coupler..:)
  6. dl324

    Distinguished Member

    Mar 30, 2015
    Using the opto coupler may be unnecessary. If you aren't loading the counter output so much that the logic HI voltage is out of tolerance you can drive your OR gate with 'e' inverted.

    Retired here too, but not quite senior yet...
  7. cornishlad

    Thread Starter Member

    Jul 31, 2013
    Thanks for that...I'm getting close to bread-boarding it, so will find out in practice if the segment drive voltages work ok as logic levels. It obviously did for the creator of the circuit I linked to but I had read somewhere it wouldn't - or you shouldn't do it..Depends on the 7 segment displays and the required brightness I guess..I'll give it a try...