CD4011BE static sensitivity
- Thread starter Rissy
- Start date
RRITESH KAKKAR
- Joined Jun 29, 2010
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Hello,
I have used ULN2003 yes it work as follow.
the input at in1 at 5v will give out 1 sink/gnd
It has been mentioned, but static control measures are no joke.
It is possible that some step of your handling is zapping chips. You do not have to feel a discharge for it to be enough to ruin a chip. Wood is static neutral, unless it is coated with polypropylene or some other polish, in which case it becomes a definite hazard. Static neutral is not the same as static safe, it can also be a hazard, it is just less likely.
Have you read this from the ebook on AAC?
ElectroStatic Discharge
Wendy's Index
It is possible that some step of your handling is zapping chips. You do not have to feel a discharge for it to be enough to ruin a chip. Wood is static neutral, unless it is coated with polypropylene or some other polish, in which case it becomes a definite hazard. Static neutral is not the same as static safe, it can also be a hazard, it is just less likely.
Have you read this from the ebook on AAC?
ElectroStatic Discharge
Wendy's Index
***ALL*** logic devices, from the lowly 4011 to an Intel quad-core CPU, stem from the inverter, or NOT function. The internal schematics on logic gate datasheets show this very clearly, although I think TTL schematics are easier to read than CMOS. Here is the basic 2-input NOR function. This is called a "wired-NOR" connection. Additional inputs are had by adding more input sections to the pull up resistor. Thanks to De Morgan's Theorem, it is equivalent to an inverted-input AND gate. Double-inverting the inputs makes it an AND gate, adding a section to the output makes that a NAND gate, etc.
This is not the perfect logic device for everything, but when you need a little combinatorial stuff in an electrically harsh environment, this technique is almost indestructible. Your original circuit reduces to two 2-input gates, with three linear regulators to protect them plus another one to power them. The 2003 enables a less complex solution. Note that in the schematic in post #41, the three input protection zeners probably are not needed.
ak
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thanks. sounds complicated.
How would one derive the following from the ULN2003?
A NOT gate
A AND gate
A OR gate
...can you reduce the the drawing of each gate into how each gate would be created by wiring up the darlington pairs of the ULN2003?
for example, how would one wire up the chip, drawing it up like this...?
How would one derive the following from the ULN2003?
A NOT gate
A AND gate
A OR gate
...can you reduce the the drawing of each gate into how each gate would be created by wiring up the darlington pairs of the ULN2003?
for example, how would one wire up the chip, drawing it up like this...?
Attachments
Given that you have logic gates in your design, I'm a bit surprised by your response. Let's back up a bit and get a handle on your skill set. In your schematic in post #22, what are the functions of U4, U5, U7, and U8? I know they are wired as inverters (NOT gates), but what function do they serve in your circuit?
ak
ak
My response is due to the fact i've never created logic gates using only NOT gates. I had to create NOT gates from NAND gates, and that was easy as the solution for this was all over the internet. It seems to be a harder deal using only NOT gates as I can't google for a solution.
The circuit i put up isn't my true or full circuit. I'm just trying to figure out how to drive ANY logic using the correct principles, that's all.
People wanted a circuit to comment on, so i gave them a circuit. But what i'm really trying to get answers to, is the answers to my direct questions, so that I can apply my learning to produce any circuit, with any logic. if that makes sense.
The circuit i put up isn't my true or full circuit. I'm just trying to figure out how to drive ANY logic using the correct principles, that's all.
People wanted a circuit to comment on, so i gave them a circuit. But what i'm really trying to get answers to, is the answers to my direct questions, so that I can apply my learning to produce any circuit, with any logic. if that makes sense.
Unless your circuit does something unusual I would say it was a purchasing problem. Are you up to building a simple circuit to test the parts when you receive them?
As you learn more about logic structures, it is important to understand that what a logic function does and how it does it are two separate things. Here is a brief introduction to wired logic, logic functions that do not use transistors:
https://en.wikipedia.org/wiki/Wired_logic_connection
Only two gate types are shown because without an active element, inversion is not possible, and this severely limits the complexity of the logical systems that can be realized. Most TTL and CMOS logic gates have totem-pole output stages, outputs that can both source and sink current. Because of this, a direct connection together of two outputs is almost always forbidden because if one output is high while the other is low, the two combined are trying to short out the system power source. On the other hand, output stages that are open collector or open drain do not have this conflict because the pull-up function is served by a resistor, not a transistor, and a resistor is an inherent current limiter. Open collector (OC) logic can not do anything more than what normal gates can do in terms of the number of different logic functions or the complexity of large logic systems, and OC logic usually is slower in terms of propagation delay and transition times. But because combining the outputs of two or more gates sometimes can be done with a direct connection rather than with another gate, it can use fewer parts, or device technologies other than TTL and CMOS, technologies that are more reliable, have higher output current capabilities, etc.
Once you have a basic logic drawing for your system using generic gate symbols, the next step is to optimize the design. Usually there are opportunities to combine some of the gate functions into gates with larger inputs, or combine logic functions with De Morgan's Theorem. It is an essential tool in logic design, and works like this.
Start with two gate types, AND and OR, and two input and output types, true and inverted (shown with the little circle or bubble). De Morgan showed that AND and OR gates can be interchanged if you change all of the bubbles. For example, a positive logic NAND gate is shown with a bubble on its output and no bubbles on its inputs because the output is false (low) when inputs A AND B are true (high). The De Morgan equivalent of this is an inverted-input OR gate, an OR gate with bubbles on both inputs and no bubble on the output; the output is true (high) when inputs A OR B are false (low). The same part represents two different logic functions, one for positive-true inputs and one for negative-true inputs. This can be handy in making your drawing show the true nature of the logic you are designing.
ak
https://en.wikipedia.org/wiki/Wired_logic_connection
Only two gate types are shown because without an active element, inversion is not possible, and this severely limits the complexity of the logical systems that can be realized. Most TTL and CMOS logic gates have totem-pole output stages, outputs that can both source and sink current. Because of this, a direct connection together of two outputs is almost always forbidden because if one output is high while the other is low, the two combined are trying to short out the system power source. On the other hand, output stages that are open collector or open drain do not have this conflict because the pull-up function is served by a resistor, not a transistor, and a resistor is an inherent current limiter. Open collector (OC) logic can not do anything more than what normal gates can do in terms of the number of different logic functions or the complexity of large logic systems, and OC logic usually is slower in terms of propagation delay and transition times. But because combining the outputs of two or more gates sometimes can be done with a direct connection rather than with another gate, it can use fewer parts, or device technologies other than TTL and CMOS, technologies that are more reliable, have higher output current capabilities, etc.
Once you have a basic logic drawing for your system using generic gate symbols, the next step is to optimize the design. Usually there are opportunities to combine some of the gate functions into gates with larger inputs, or combine logic functions with De Morgan's Theorem. It is an essential tool in logic design, and works like this.
Start with two gate types, AND and OR, and two input and output types, true and inverted (shown with the little circle or bubble). De Morgan showed that AND and OR gates can be interchanged if you change all of the bubbles. For example, a positive logic NAND gate is shown with a bubble on its output and no bubbles on its inputs because the output is false (low) when inputs A AND B are true (high). The De Morgan equivalent of this is an inverted-input OR gate, an OR gate with bubbles on both inputs and no bubble on the output; the output is true (high) when inputs A OR B are false (low). The same part represents two different logic functions, one for positive-true inputs and one for negative-true inputs. This can be handy in making your drawing show the true nature of the logic you are designing.
ak
Three 7809's? Exactly what voltages are they putting out? At no time does an input voltage exceed power to the chip?
Re: incoming testing of parts
Just a suggestion, but are you sure the chips are good when you get them? Consider a simple test fixture with a general purpose design that could be used for testing many different chips?
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Sorry for the delay in my response, the run up to xmas, work and going to the gym is taking its toll on my time lol!
I did exactly this, just putting each NAND chip on some breadboard and made sure each gate was energised or tied to ground in all their permutations and with a multi meter in each configuration, i checked the outputs. Each output had the correct (expected) outputs according to each scenario, and i kept those chips. Anything which didn't pass this test, got thrown in the bucket.
Weirdly enough though, even the ones which passed, then still wouldn't work on my proper circuit which is only ever worked with these other two which have proven to be the only ones to ever work on my circuit. So i'm then only led to one conclusion. My proof test isn't correct for testing these chips. My only thought is that i was not loading the outputs, and therefore getting a false positive outcome from the "successfully tested" gates....?!
The 7809's take in the 12-1V automotive voltage i want to put into my logic circuit, and convert it down to a stable 9V. I'm using one for the VDD source, and i'm using one on each "input", which is obviously running at the same automotive 12-14V. They seem to be behaving, doing what I want them to do, at least on my kitchen power supply, kicking out 12V. The source power is there all the time, and then the inputs are switched on and off, so the source will always be there first.
I was looking at chinese CMOS testers, which come in at around £25-£30 an have a 6-week lead time on delivery. I didn't know how to make my own. I guess i need to do something, as i'm throwing away lots of these chips which i'm convinced aren't working, because they wont work on my circuit, which i've proven with two chips only, but i want four to work in total in the end...
I appreciate your help and advice on this circuit on post #22. But i must stress, it's a made up circuit, just to get my point across for a generalisation of what i'm trying to do. I rushed that circuit together, without paying much attention to what it was actually doing. I just want to get across the point that i'm trying to work some logic based on inputs switching on and off, with maybe one thrown in there of a pulsing nature. So don't concentrate too much on the logic of that circuit, more the overall philosophies of what is required for any logic circuit of this nature, in an automotive environment. Once again, i appreciate your input. I just don't want you to waste any (more) time concentrating on reducing that particular logic. I started the thread more to discuss the susceptibility of these NAND chips to static.
It sounds like your test is good. Then three power sources may be the problem. Exactly what voltages are they putting out? Is there a possibility you are applying a higher voltage to an input than the power to that chip? Use the highest voltage as power to the chip.
I think the objective was to monitor the outputs of the 7809s.Are you really using those 7809 regulators like that?
Have you tried testing without the regulators?
