Hiiee
So Im studying digital electronics.I'm kind of new to the subject.
For the question,
Q:
Obtain a circuit diagram for a clocked synchronous sequential network having a single input line x, in which the symbols 0 and 1 are applied, and a single output line z. the network is to analyze each sequence of four binary digits and produce the corresponding 2’scomplement of the 4bit sequence. Assume each 4bit sequence is occurring with the least significant bit first. An example of input/output sequences that satisfy the conditions of the network specifications is
X = 0 1 0 1 0 0 0 1 1 1 0 0 0 1 0 0
Z = 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1
I got a feed back saying my state diagram is wrong. Can anyone tell me what I did wrong??
Pls find my solution as attached
So Im studying digital electronics.I'm kind of new to the subject.
For the question,
Q:
Obtain a circuit diagram for a clocked synchronous sequential network having a single input line x, in which the symbols 0 and 1 are applied, and a single output line z. the network is to analyze each sequence of four binary digits and produce the corresponding 2’scomplement of the 4bit sequence. Assume each 4bit sequence is occurring with the least significant bit first. An example of input/output sequences that satisfy the conditions of the network specifications is
X = 0 1 0 1 0 0 0 1 1 1 0 0 0 1 0 0
Z = 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1
I got a feed back saying my state diagram is wrong. Can anyone tell me what I did wrong??
Pls find my solution as attached
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