# Can you tell me if this is correct?

#### s.chirumamilla19

Joined Mar 14, 2016
4
Hiiee
So Im studying digital electronics.I'm kind of new to the subject.
For the question,
Q:
Obtain a circuit diagram for a clocked synchronous sequential network having a single input line x, in which the symbols 0 and 1 are applied, and a single output line z. the network is to analyze each sequence of four binary digits and produce the corresponding 2’s-complement of the 4-bit sequence. Assume each 4-bit sequence is occurring with the least significant bit first. An example of input/output sequences that satisfy the conditions of the network specifications is
X = 0 1 0 1 0 0 0 1 1 1 0 0 0 1 0 0
Z = 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1
I got a feed back saying my state diagram is wrong. Can anyone tell me what I did wrong??
Pls find my solution as attached

#### WBahn

Joined Mar 31, 2012
24,970
MOD NOTE: Moved to Homework Help from General Electronics Chat.

#### WBahn

Joined Mar 31, 2012
24,970
Have you walked through the given data set using your state diagram to see if it produces the correct outputs?

#### s.chirumamilla19

Joined Mar 14, 2016
4
yes it gives the correct outputs.
Is it okay to draw a feedback out of Z?

#### WBahn

Joined Mar 31, 2012
24,970
Can you explain your state diagram?

You are showing two inputs -- x and c. What is c? There is nothing in the problem statement that talks about an input c. Where is it coming from?

What do you mean "a feedback out of Z"?

#### s.chirumamilla19

Joined Mar 14, 2016
4
Im sorry. so the question says that a 2's compliment is produced for every 4 bits. lets suppose the first 4 bits of x is 1111.
then the output produced should be compliment of(1111) + 1 = 0000
+1
----------
0001 (2's compliment of x=1111)
but if the input is x=1110, then
output should be compliment of(1110) +1 = 0001
+1
----------
0010 ( here a carry c=1 is produced by adding 1+1 binary addition)
if x is0000 then twos compliment = 1111
+1
this produces a carry c=1 for each state from the previous state. Hope u got the point.

so depending on the input x, there might or might not be a carry.so if we consider each bit place as a state, depending on the previous state there might be a carry.

My friends used 8 states instead of 4. divding each state when carry=1 and carry =0. But it takes 3 flipflops to realize. What i did is I gave initially C=1 and then fedback the C from the previous states output as shown in realisation attachment.

#### WBahn

Joined Mar 31, 2012
24,970
But you do not have a 'c' signal at your disposal. If you need to store that information, then that has to be done so as a part of the state. You diagram has to be such that if I tell you what state you are in and what the value of X is, that you unambiguously know what the output should be and what state to go to next. Thus the current state has to represent ALL relevant information about the ENTIRE history of the machine.

Ya I guess that is it. But I need someone to clear that for me. Thank you so much 