Audio Pre- Amplifier Design - Please can you tell me if my theory is correct?

Discussion in 'Homework Help' started by Solar shock, Dec 4, 2014.

  1. Solar shock

    Thread Starter New Member

    Dec 4, 2014
    Hey guys, (sad face - I got an 'alert' and I just lost this post when I was 90% done, here we go again :p)

    First off, id just like to say; this is my first post, but been a occasional lurker when on the hunt for the ever elusive electronics knowledge, so a big thank you for all the help you have given me; if a little unknowingly;). I am predominately looking to consolidate my knowledge and to help it grow about my circuit; but more about that below.

    The task I was given: Audio Pre-amplifier Design

    The aim is to design and test a pre-amp circuit, with the following specifications:
    1. 300Hz to 3.4kHz bandwidth
    2. 'in-band' sensitivity of 2V/mV with a max input of +/- 15mV.
    3. 'in-band' input impedance should be well defined at 50kohm and output load min value is 2kohm.
    4. power supply is +Vcc and 0.
    What I have achieved thus far:

    I have a working circuit (well eventually i did ;)), it achieves close to a gain of 2000, the resistors on the first stage are a little out and I only get 225 instead of 250, so when multiplied by the second stage of 8, I end up with about 1800, but this is ok, as the lecturer likes stuff to be a little wrong, as then he likes to see you explain why it is so. For a 1mV input I get close to 2V out.

    It runs of a single supply, however I haven't drawn the 741's supply lines in, they go to Vcc and 0.

    What Id like help with: Can you please assess my theory of my circuit that I am about to give and then let me know where I am wrong, or areas that can be improved. I have used blue text for the areas that I feel I am most uncertain about.

    My Theory/Knowledge:
    • The input to the first stage is acting as my DC offset, due to the potential divider their is a DC component added to my AC signal in that is Vcc/2. This is what allows my 741 to swing within a positive voltage range. It also forms part of my HPF, with a total resistance of 50kohm and the 10nF capacitor I get a HPF that has F1 = 318 Hz.

    • Due to the virtual earth created by the op-amp, the negative input will attempt to make the difference between the two inputs 0, therefore the negative input will also be at the DC offset of Vcc/2. so it works like a differential amplifier and amplifies my AC input wave + and a little noise to some extent?

    • Circle 3 - I am not 100% on what this is achieving? Is this helping to remove any high frequency AC noise that is appearing on the output? by allowing it to pass to ground when the Xc gets small enough?

    • The gain of stage 1 is set by the resistors, but is not affected by the capacitor to ground in circle 3? surely at lower frequencies (for example Xc = 4k at 400Hz) the Xc is adjusting the gain of stage 1; as R2 is now effectively 2.2k + Xc?

    • Circle 1 - Acts as DC blocking; removing any DC offset including any DC offset errors introduced by the op-amp. It also affects the gain of the second stage; as its Xc value affects the resistance total of R4. ( i found this out, as originally I used a 0.1uF, and found that my Xc at 1500Hz was about 1k, therefore my R4 was about 2.2k, and my output was about half of what I was expecting) - Is that correct? I believe its right, as i solved the issue by making it the 1uF which gave me a much lower Xc which then had a much lower impact on R4 and thus the gain of the second stage.)

    • The DC offset is then reintroducted on the positive input of the second stage, again due to the inputs wanting to be equal the negative input is also then up at Vcc/2.

    • Circle 2 - This capacitor is acting purely as de-coupling, its there to remove any AC noise that may have gotten onto the supply rails; as this noise would then be amplified / affect the amplification of my wanted signal?
    Any extra questions I have:
    I have found that the bandwidth is actually about 600Hz to 2.8kHz. Is this reduction due to the capacitors in my circuit?

    Hey guys, well if you made it this far then thank you for taking the time to read my rather long post. I would ideally like to discuss the answers rather than be given them, so keywords, or areas I should go look up would be greatly appreciated, as I need to write my report on this circuit. I also have quite a few books at my disposal; operational amplifiers by G clayton, op amps for everyone by B carter. So if there is a topic in there I should consult please let me know.

    also any knowledge that im completely missing or questions you have do say!

    Kindest Regards

    Pre-amp paint schematic.jpg
  2. Jony130

    AAC Fanatic!

    Feb 17, 2009
    All your capacitors except capacitor in circle 2 has a effect on the amplifier bandwidth.
    Circle 3 capacitor is needed because the op-amp is supply from a single power supply. So we need to bias the op amp somewhere in the middle of his "linear region". This is a job for input voltage divider (Ra, Rb). Without the capacitor the output DC voltage will be equal to Vcc (positive sat voltage). But we have this capacitor in the circuit, so DC voltage gain is reduce to one. And the output voltage is equal to 6V.
    Also this capacitor from a filter with R2 resistor. Fc = 0.16/R*C = 0.16/(2.2kΩ * 100nF) = 728Hz

    Circle 1 capacitor with R4 also form a high pass filter, Fc = 0.16/R*C = 0.16/(1.2k * 1μ) = 133Hz

    Circle 2 has now influence amplifier bandwidth. But you should add 10μF or larger capacitor parallel to 0.1μF = 100nF.

    Input capacitor (10nF) also is a high pass filter. Fc = 0.16/(Rb||Ra * Cin ) = 0.16/(50kΩ * 10nF) = 320Hz

    And finally 4.7nF capacitor with R3 forms low pass filter, F = 0.16/(10kΩ*4.7nF) = 3.4khz

    So if you want 300Hz to 3.4kHz bandwidth set all high pass filter at 30Hz or lower except Cin with Ra and Rb.
    This filter set to F = 0.16/(Cin * Ra||Rb) = 300Hz.

    Also notice that your opamp is very old and has a gain bandwidth product around 1Mhz. Additional your first stage amp will have a very large gain (1 +R1/R2 = 255V/V) so the bandwidth of this stage is reduce to F = 1Mhz/255 = 3.9kHz.
    And this is why your measured upper frequency limit is at 2.8Khz instead of 3.4khz. So to reduce this effect try set 0.16/(10kΩ*4.7nF) at 4.2khz or larger.
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  3. Solar shock

    Thread Starter New Member

    Dec 4, 2014
    Thanks for the response, I think I understand most of it, but there are some areas I am not sure of;

    I am still unsure what capacitor in circle 3 is doing - As is it not capacitor in circle 1 that is blocking the DC component from the input of the second stage?

    I thought that to create a filter with the resistor the setup had to be with one of them in parallel with respect to the Vout?

    See I thought that it was this capacitor that was doing the blocking of the DC offset in the stage 1 output. The capacitor would act as a high pass filter to some extent due to its reactance at low frequencies (so at low frequencies the reactance attenuates the signal), but at the same time it acts to completely block the DC component of the output of stage 1. This is important then, as it prevents the DC bias of the stage 1 affecting the DC bias of stage 2.

    Ok, why do you suggest I add another capacitor in parallel to the 0.1uF? surely that would just give me a combined capacitance of: 10uF + 0.1uF? So the additonal capacitor would be almost un affected by the original already there? Why would that be any different from simply replacing it with a 10uF?

    Input capacitor (10nF) also is a high pass filter. Fc = 0.16/(Rb||Ra * Cin ) = 0.16/(50kΩ * 10nF) = 320Hz

    And finally 4.7nF capacitor with R3 forms low pass filter, F = 0.16/(10kΩ*4.7nF) = 3.4khz.[/QUOTE]

    Yep, completely get that :)

    Ah ok, so with this your saying, to ensure that I keep the bandwidth at the levels I want I need to make sure that all of the high pass filters are only filtering below the value of the HPF at the input. I get that, makes logical sense :)

    I understand how you calculated the bandwidth of the stage 1 being 3.9kHz, but why does that mean the upper frequency limit is at 2.8kHz?
    Surely if the upper limit is 3.9kHz and I am trying to achieve 3.4 that is ok? Or is it then to do with the tolerances of my op-amp? so that while theoretically I should be able to achieve 3.9kHz, in reality the GBP of the op-amp isn't quite 1MHz, so with my gain remaining at 255, I am then having to sacrifice the bandwidth?

    So like you suggested, to deal with that I should reduce the gain of the first stage, thus reducing the fact that I am at the GBP limit of the chip, allowing me my bandwidth?
  4. Jony130

    AAC Fanatic!

    Feb 17, 2009
    Cin capacitor remove a DC component from the input signal only. But don't forget that Ra and Rb bias the op amp somewhere in the middle of his "linear region" Vcc/2. And this DC voltage is present at the non-inverting input. So we add C3 (circle 3) into the circuit, because we don't want to amplify any DC voltage present at the input of the amplifier. Without C3, any DC voltage present at the "+" input will also be amplified (1+ R1/R2) times. So by adding C3 we "reduce" DC voltage gain to one.
    Look at this example


    For DC signals and for low frequency Xc ≈ ∞. And this is why DC gain is 1V/V (1 + R1/(R2 + Xc)).
    But as frequency rise, Xc decrease his value. And at frequency (F1) when Xc = (R1 + R2) amplifier gain start to rise from 1V/V and will reach 11V/V at frequency (F2) when Xc = R2. In reality the gain at F2 is -3dB lower from 11V/V (0.707*11V/V = 7.7V/V). The gain will reach 11V/V at 10*F2.

    Because we want to short any signal present at this input to ground.
    For example, without C2 any noise from Vcc will appear at the "+" input. And this noise will also be amplified by the amplifier gain (1 + R3/R4). So we add C2 to short any AC voltage present at the amp input.

    As for the remaining part of the question please read this (why 100nF||10μF)

    Your upper frequency limit is at 2.8kHz because you have two low pass filter whose upper critical frequencies of each stage are all almost the same (3.9k and 3.4k), and this is why the dominant upper critical frequency is reduced by a factor of 0.643 or so. So what you can do is to split the gains in half between two stages. Set the gain of each stage equal to √2000 ≈ 45V/V.
    Also don't forget that you need coupling capacitor at the output also. And this capacitor also from high pass filter with the load resistance.