Generally, I tie CE to ground and only lower WE when writing data to an EEPROM. Now I have an MX7528 DAC with WE and CE inputs which function like EEPROM WE and CE inputs. Would the write operation still work if I tied WE and CE together and put them both low at the same time for write operation and put both high at the same time for no operation? or is there something I need to worry about when using both lines this way?

 

Which eeprom are you using?

 

Read the datasheet very, very carefully to see if there are setup time requirements, such as CE must go low 20 ns. prior to WE going low. If you find a statement to the effect that the setup time is zero you are good on the front end. Then look for a hold time requirement, such as WE must go high 10 ns. before CE goes high. If you find that the hold time is zero then you can try it to see if it works. If either one is non-zero you can try it, but don't come here complaining that it works sometimes and not others.

 

Would the write operation still work if I tied WE and CE together and put them both low at the same time for write operation and put both high at the same time for no operation?

Won't work. CE must go high at least 10nS after WE goes high.

 

I'm asking specifically for the MX7528 DAC because it has a WE and CE pin on it.

 

The DAC is transparent when both /WE and /CE are both held low. The data is latched when either goes high.

Go ahead and tie the two together and see if it works.

 

I'm asking specifically for the MX7528 DAC because it has a WE and CE pin on it.

Not guaranteed to work.




Chip Select to Write Hold Time is 10nS minimum.

 

@dl324
I saw your first response and saw the tCH 10ns Chip Select to Write Hold Time in the datasheet.
I don't know what this means (meaning I don't know why they quoted this spec).
This is inconsistent with the information stated in the text.

 

@dl324
What you said should be in the normal operation, but if you choose the Write Mode then it could be a little difference.



Mx7528 datasheet page 8.

 

if you choose the Write Mode then it could be a little difference.

I posted the Write Cycle Timing Diagram from the datasheet.

I always trust the timing diagram(s) more than the descriptions. I've never seen a description in words that contained the same detail.

The timing diagram shows that CS', DACA'/DACB, and DATAIN must be held for 10nS after the rising edge of WR'. None of those requirements are described in the Write Mode text description. It also doesn't give the timing requirements for how long signals must be asserted.

If you choose to ignore timing specs, it might not work for all (or any) parts.

 

@dl324
I do not dispute anything you have posted so far. What I do question is the datasheet specification of 10ns for tCH.

tDH is also spec'd at 10ns. That I can understand.

I would expect that internally in the CONTROL LOGIC there is some form of AND condition of CS and WR. When either of these is FALSE the data is latched. Hence tCH becomes irrelevant.

 

I posted the Write Cycle Timing Diagram from the datasheet.

I always trust the timing diagram(s) more than the descriptions. I've never seen a description in words that contained the same detail.

The timing diagram shows that CS', DACA'/DACB, and DATAIN must be held for 10nS after the rising edge of WR'. None of those requirements are described in the Write Mode text description. It also doesn't give the timing requirements for how long signals must be asserted.

If you choose to ignore timing specs, it might not work for all (or any) parts.

One ic can be use many ways as different mode like this ic, I'm not guarantee that it would be works, but that is wrote in the datasheet, if the TS can test it then it's easy to prove it.

 

What I do question is the datasheet specification of 10ns for tCH.

Unless the schematic for the part is available, we have no way to analyze circuit delays and have to go by what the manufacturer guarantees will work.

That being said, for any lot of devices, there will be manufacturing variances that will cause some devices to be faster or slower than others. Manufacturer specs take this into consideration as any falling outside of their published specs will be rejected or down/up binned and sold as a different speed part.

 

if the TS can test it then it's easy to prove it.

That might be acceptable for a one off type of design. If the part ever needed to be replaced, it would need to be replaced with a part that had been screened for the out-of-spec parameter necessary for the circuit to function. That's a poor design practice, but people can do whatever they want for their own personal consumption.

 

That might be acceptable for a one off type of design. If the part ever needed to be replaced, it would need to be replaced with a part that had been screened for the out-of-spec parameter necessary for the circuit to function. That's a poor design practice, but people can do whatever they want for their own personal consumption.

If the design nothing with multifunction then it's easy to play with, some pins can be easy to connected together.