i would appreciate any help on this..and if this is possible plz tell me how...

 

Yes it is possible. The processor fetches two bytes from memory into the instruction register and takes another cycle to execute the instruction. That's how.

 

Or for that matter take a look at the architecture of any of PIC18F microcontrollers.
They have an instruction bus that is 16 bit wide but their data bus is only 8 bits wide.

 

thanks a lot..but can i know what is the relation between the instruction decoder and instruction size ??
and can i know abt the concept of opcode?

 

The only way to know is to look it up in data sheet for the processor that you are using. Every family of processor has its own way of doing things and there are no general rules.

 

There are two primary architecture types referred to as "Princeton" and "Harvard" after the universities where they were developed.

In the "Princeton" architecture all instructions and data resides in a single common memory of a certain size and width. For example 64K (65,536) bytes long and 8 bits wide. The 8 and 32 bit AVR families are examples.

In the "Harvard" architecture the instructions and data reside in separate memories which can be different sizes and widths. The PIC18F family is an example of this.

As far as the "instruction register" is concerned it may or may not be the same width as the memory from which the instructions are fetched. Usually all the elements of an instruction are present in the instruction register before decoding happens. There is nothing wrong with making multiple accesses to the memory to load the instruction register, and in the other direction there is nothing wrong with pulling multiple instructions from memory into a pipeline for dispatching to the instruction register.

 

Usually all the elements of an instruction are present in the instruction register before decoding happens.

do not want to be rude...but would like to ask u when u say "USUALLY", is there a case in which same instruction is decoded in two parts?


one more question.. for a 8-bit processor how many number of instructions possible...

can i have more than 256 instructions?

 

It is possible to have more than 256, but I don't think it has been done. Often the instruction will be composed of the operation, the source and the destination that the operation will work with.
Most of the instructions on the PIC12F675 follow this pattern, but there are a few operations where longer constants are used and a few with no constants, but the number of bits stays at 14.
This 14 bit instruction is composed of 6 bits for the operation.
It also uses either :
7 bits to specify which bit of memory the operation works on and 1 bit to specify if the result goes there or to a working register.
or:
8 bits for a constant to use with the operation.

 

do not want to be rude...but would like to ask u when u say "USUALLY", is there a case in which same instruction is decoded in two parts?


one more question.. for a 8-bit processor how many number of instructions possible...

can i have more than 256 instructions?

I say usually because there may be an example somewhere that decodes instructions in pieces.

In a processor with an 8 bit wide ALU the number of instructions can be more than 256 if multi-byte instructions are allowed. The 8085, Z80, 8086, 6809, 68HC11 are all examples of how this works.

 

Z80, besides 1 and 2-byte instructions, even has a number of 4-byte instructions (I don't remember for sure, but it probably has 3-byte instructions too).

 

thanks alll................................

 

The JMP and CALL instructions on a Z80 are both three bytes long.

 

I think it perhaps correct to distinguish between the opcode and the operand(s). On the Z80 the JP nn is 3 byte long. the Opcode is (C3) is one byte long. But the Z80 has several two byte opcode instructions. Like the the Return form interrupt (RETI) or the Return form nonmaskable interrupt(RETN), as some examples. The opcode is ED4D, or ED45. If a Z80 opcode starts with ED, it will always be two byte long

 

This is an interesting point. I think we drifted from "opcode" to "instruction" possibly without realizing it. This distinction would have a bearing on weather the execution could begin before the complete instruction had been fetched. For that you would need a cycle by cycle breakdown of each instruction. I've seen this done for Motorola processors but seldom for any others. My impression is that execution requires the complete instruction, but I could be wrong.

 

The opcode is ED4D, or ED45. If a Z80 opcode starts with ED, it will always be two byte long

great...i think this was my very doubt..i will reframe it...if the data-bus width is 8 bit ..can we have instructions more than 256..i.e. can an opcode of value more than FFh be possible for this ??

 

It was at least so on the Z80, and I guess also on other 8 bits CPUs from this time period. But my experience is limeted to Z80

 

I already gave a partial list of ones besides the Z80. I'm not sure the 8085 qualifies as having more than 256 "opcodes"

 

is there any way in which we can program the instruction decoder to work differently than it normally will ??

 

I have not seen any off the shelf microprocessors or microcontrollers where this was possible. Some machines of an earlier generation were micoprogrammed and this was possible. If you want to do your own you can with a development kit from Xilinx or Altera

 

great...i think this was my very doubt..i will reframe it...if the data-bus width is 8 bit ..can we have instructions more than 256..i.e. can an opcode of value more than FFh be possible for this ??

I think this turns into a semantic question... It depends on what you mean by 'opcode' (it depends on what the meaning of 'is' is).

A single byte fetch from memory, will bring in a value of 8-bits, the value of which is between 0x00 and 0xFF, giving only the possibility of 256 different outcomes.

Some of these outcomes may be to do something immediately, usually simple things like AND a resident register with itself and return the results to the same register. Not much info needed to do that simple task.

Some of these 256 outcomes may be to do a subset of instructions that need more info, i.e. fetch another value from memory. Things like load a register with some user defined immediate value, that value being the next byte in memory. Is this part of the 'opcode'? If it was a PIC or equivalent, the immediate value would be embedded in the extended length instruction/opcode, so I would argue that on the 8-bit, even though it was a separate fetch, it is still part of the instruction. This interpretation lets you compare bananas to bananas.

Yet some others of the original 256 outcomes may say to get 2 more bytes, like the absolute jumps of the Z80. To jump to a 16-bit address, you need to know what all 16 bits are.

Again, the example of the Z80, there can be modifiers to extend the instruction even further, when things like modifying or testing a particular bit of a value in memory pointed to by an index pointer plus an absolute offset (whew!). 4 bytes, but only for the most esoteric instructions. Many of these are the ones that are left out or changed in the Rabbit variation of the Z80.

You could potentially have this nested 'fetch another byte to get the rest of the instruction' go on for as many bytes as you want.

In the multi-byte instructions, not all of the bytes are technically called opcodes, but if you are comparing them with the same thing on something like a PIC, then they probably should be considered to be the same thing.

256 'first choices', virtually unlimited total number of choices.