Cadence Pspice error - Incorrect number of interface nodes for x1

Thread Starter

Saikumar Natarajan

Joined May 17, 2017
1
Here i'm trying to run the netlist to perform I-V characteristics of a MOS transistor. I am getting this error "Incorrect number of interface nodes for x1". Can someone provide inputs on this?

.SUBCKT BSS138W drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0

.PARAM Rs=0.054 Rg=25 Ls=3n Ld=1n Lg=3n
.PARAM Inn=0.2 Unn=10 Rmax=3.5
.PARAM act=0.13

X1 d1 g s Tj K_60_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn}
+Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1

Rg g1 g {Rg}
Lg gate g1 {Lg*if(dgfs==99,0,1)}
Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))}
Rsa s1 s 1Meg
Ls source s1 {Ls*if(dgfs==99,0,1)}
Ld drain d1 {Ld*if(dgfs==99,0,1)}

Rth1 Tj t1 {414.65m+limit(Zthtype,0,1)*153.45m}
Rth2 t1 t2 {1.8+limit(Zthtype,0,1)*672.5m}
Rth3 t2 t3 {7.56+limit(Zthtype,0,1)*3.62}
Rth4 t3 t4 {41.47+limit(Zthtype,0,1)*17.99}
Rth5 t4 Tcase {25.33+limit(Zthtype,0,1)*10.99}
Cth1 Tj 0 1.508u
Cth2 t1 0 2.286u
Cth3 t2 0 15.089u
Cth4 t3 0 394.032u
Cth5 t4 0 3m


.ENDS
*$


.option tnom=27
.temp 27

x1 net_4 net_2 0 net_11 BSS138W
***** m1 net_4 net_2 0 net_11 IXKK85N60C m=6 ********
*+ m=1
*+ L=5e-6
*+ W=300e-6
*+l=2u
*+w=860u
.MODEL nmosx NMOS
+ LEVEL=3 VERSION=3.22
+ TOX=1.9800000E-08 XJ=0.2U NSUB=4.9999999E+16
+ CJ=4.091E-4 MJ=0.307 PB=1.0
+ CJSW=3.078E-10 MJSW=1.0E-2
+ CGSO=3.93E-10 CGDO=3.93E-10


.MODEL IXKK85N60C NMOS
+ LEVEL=3
+ L=2.0000E-6
+ W=860
+ KP=1.0387E-6
+ RS=10.000E-3
+ RD=19.626E-3
+ VTO=3.4544
+ RDS=12.000E6
+ TOX=2.0000E-6
+ CGSO=11.628E-18
+ CGDO=729.90E-15
+ CBD=80.669E-9
+ MJ=1.1673
+ PB=3
+ RG=10.000E-3
+ IS=21.329E-6
+ N=2.3569
+ RB=1.0000E-9
+nfs=0.2e12

*.param L = 1
*r1 net_9 net_2 10k
*e_test net_9 0 value = { {L} * 1}

*xm1 net_4 net_2 0 BUK9637-100E


*x1 net_4 net_2 0 IPB107N20N3_L1

vg net_2 0 DC=0
vd net_1 0 DC=0

v46 net_1 net_4 0
v47 net_11 0 dc=-.1
*v48 net_12 0 dc=0

*.option gmin=1e-12


*V55 net_55 0 DC=0.01
*C54 net_54 0 1e-12
* end toplevel circuit
.DC
+ vd 0 25 0.5
+ vg -1 10 .5



.probe I(V46) I(V47)
*I(v48)



.END
 
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