Cache's manipulation mechanism

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Joined Mar 8, 2019
Hello !
I've already studied the subjects of Cache manipulation, and how we store into the Cache by which mechanism and how actually it goes behind.
I've a homework and I'm not asking to solve me it because it's already solved, what I'm asking to clear out for me why they solved it in this way and why answers like this, I'm not understanding at all why answers like what they solved, so it would be appreciated if you guys help me how they fill the tables of the questions to understand what's going on!
given a processor with 32bit that's connected to Cache, size of the Cache 256Byte, size of the block is 16Byte, the Cache satisfy direct mapped, write back, write allocate. the Cache connected to main memory by 32 bus(32bit), time of access to the cache is one cycle.

(a) fill the tag and index, offset, calculate the cache size, number of tag's comparators. (( by the way how do we calculate the number of comparators? and how we know when we consider a dirty bit and valid bit? ))
(b) fill the table with miss or hit and calculate AMAT
(c)given that Cache is now two way set associative instead of direct mapped, LRU exchange.
(d)given that Cache is now fully associative instead of direct mapped, LRU exchange.

** the question is already solved but I need to understand how they solved it and what's the differences between mechanisms of cache's manipulations **
I'm attaching the photos, its order from left to write corresponded to (a) ------> (d)


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