This is one question which complelety fuzzy my head & I never get exact answer:


1. Here a website which says select bypass cap depends upon internal freq basis also.
http://www.edn.com/article/474202-Bypass_capacitors_no_black_magic_here.php



2. Some web says, need not to take internal caps freq into consideration, only factor is how much load you drive:
it has differenr factors
http://www.interfacebus.com/Design_Capacitors.html#f



Can someone shed more light on it.

 

General rule of thumb: put a 0.1uF cap at every chip, as close as possible to the power supply pin and ground pin.

Depending on the application and the chip, place a 2.2-10uF electrolytic tantalum beside the 0.1 uF cap.

Again, depending on the application and size of the board, one or two of the electrolytic caps might do for the whole board.

 

There are many factors to consider such as the size and component density of the board and what frequencies are involved -- the higher the frequencies, the more bypassing can be required. If you want to be exact, you can calculate the ESR/inductance of the power traces and determine the resonances for successive values of capacitance that need to be placed.

However, generally, you should bypass each power form as it enters the board with a properly sized series ferrite bead and capacitors forming a pi filter (if power is external). Then, place larger caps (47uF - 470uF) around the board at strategic locations, and place an additional 1uF to 4.7uF cap especially near power hogs (along with below).

All devices should have at least a 0.1uF (I use 0.22uF) near each and every power pin. Add 1000pf and 100pf (or something near those decades) if it is a higher operating frequency device. You may also want to add a series ferrite bead to such devices (such as power into an ADC) to prevent power interference to other circuits.

Sometime you may want to create equal but separate power forms, such as +5VA (analog) and +5VD (digital) from say +8V, to keep digital noise off the analog circuits.

The use of ground planes and power planes next to each other also helps (for multilayer boards), and divide the board in half between digital and analog as best as practical in relation to power entry and I/O signal connectors.

Allocate plenty of GND pins on connectors, don't just consider current required; a GND per each signal is best, but not always practical, reducing the quantity of GND pins may be necessary to a certain extent. Don't clump GND pins together, spread them out across a given connector.