I have to design a BJT amplifier for a class lab, using a voltage divider circuit. In the diagram below we can only choose the values of the Capacitors Ci, Co and Ce and the resistors R1, R2, Rc and Re. Also, the signal generator will not allow you to get anything lower than a 120 mV p-p input signal, which sucks.

(Edit: I just noticed that I left out the ground reference and that the capacitor at the input is backwards in this image.)

I've been biasing the transistor (which incidentally has an hFE of 160) at different Q points, all of them very close to 6V, or half the power supply voltage (which we also can't change). The problem is that I get a distorted output signal where the positive cycle is wider than the negative one. Pretty much like in this image:

Now, this seems to be a common issue with this configuration, as there is no negative feedback in the emitter, and I did find a good thread where a similar question is asked (http://forum.allaboutcircuits.com/showthread.php?t=38466). I am convinced that this is a result of the nonlinear relationship between changes in Vbe and the corresponding change in Ic. (There seemed to be a little debate on this in that thread but the nonlinearity explanation seems to be the consensus in different sources as well as in http://highered.mcgraw-hill.com/sites/dl/free/007252362x/302747/Chapter_6.pdf pages 373-376).

The question is, are there any methods for determining an optimal Q point where the distortion is minimal? Or just any other ideas that may help towards decreasing the distortion, keeping in mind that the configuration cannot be changed. I have tried with different Icq's like 1mA, 6mA and 10mA but to no avail.

Thanks.

 

The harder you drive the input the greater the output distortion - essentially for the reasons you mention - including non-linearity over the increased dynamic range. Nothing is perfect unfortunately, so the designer tries to keep the function within the region providing acceptable levels of distortion.

You can include emitter feedback to reduce distortion for a given input / base drive level - but you pay the 'penalty' of reduced stage gain. You should be able to test this in your simulation by splitting Re into two components and bypassing only one of them with Ce.

 

Hi,

From the graph, it looks like your trying to squeeze out as much gain as you can,
Lower the gain a little and don't worry about the collector current for this design,
since your parameters are mainly with the input voltage, work from there out.

Start by making your base voltage considerably much higher than the p-p input signal.

then work from there to the front of your stage with an appropriate output voltage.

Also make sure to keep the input impedance high enough so as to not distort the input signal as well.



I also built the circuit on a breadboard to verify this.

Distortion set in when the input peak voltage went past 180mV.

Some times a design has to start in other places of the stage to accomodate restrictions to the design.

 

You're over driving the input signal. Constrain the input to 10mV. Otherwise you get the distortion you described. Remember the small signal approximation is constrained to a small input voltage. To remedy this in your lab use a two resistor voltage divider before the input to your overall amplifier. Say 10k and 1k for a factor of 10. Then your output should be linear.

 

If you are not allowed to attenuate the input signal (with a voltage divider), you can let Ce=0, which will allow you to handle the 120mV signal with less distortion, but less gain.

Do you have an assigned gain target?

 

Well, I forgot to mention that we have to make Ce bigger than Ci and Co, and neither can be zero or negative (for generality lol).

I'm going to bias it as hobbyist suggested, making Vb >> Vs. But, if I use the rule of thumb for taking 10x as a good approximation to >> that I've seen in many places, wouldn't that yield (10)(120 mV p-p) = 1.2 V? I don't think that's less than any biasing I've done on the transistor.

I don't have an assigned gain target, but I may be able to get a hold of some different signal generator that gives me a smaller signal (I just discovered there are some in the school lab that will let me get a 10 mV p-p signal =] ).

 

I came up with using around 1.5 to 2v. for the base voltage.

I used around 2mA. for collector current.

Even with this low of current the gain still came out as (2.5v. / 120mV) ~= 20.
Due to a smallish CE so as to not overdrive the amp output, as well as keeping Zin higher, which prevents input signal distortion.

One thing to check when designing an amp stage, you showed the output signal distortion, however always check the input signal as well, if the input signal has distortion, then you know right out, that the input impedance to the amp stage is too low for the signal source to work into properly, so first work on the Zin of the stage to correct that part, then once you have nondistortion at the input, then concentrate on the stage output.

You don't have to look for another signal source with lower output voltage, think it through and work with it as a design challenge.

Here is a schem. that works ONLY with a low supply voltage of 6v, (it won't work at 12v.)
Using the same input voltage of 120mV. pk.

By using the right values for resistors and voltages to bias the stage you should be able to design for a signal input as given with no distortion.
Be creative in your design, such as choosing input signal freqencies that can colaborate with your choice of capacitors...ect...



Hope this helps give you confidence in this project.

 

Thanks for the help. I've tried to follow your advice and simulated a number of DC bias configurations but I can't get a low enough level of distortion even at 100 mV p-p in the medium frecuencies.

The example you provided looks a little contrived as the voltage source is set at 2 KHz where the very low 0.1 uF capacitor in the emitter will have a high reactance.

Is it just impossible to get low distortion with a ~120 mV p-p input signal and no feedback in the emitter? Does anybody know how you can model the distortion based on biasing parameters and input signal amplitude?

 

Does anybody know how you can model the distortion based on biasing parameters and input signal amplitude?

That's why we go to simulation methods - it's too time-consuming otherwise.

One could presumably use graphical techniques which include careful (=tedious) plotting and mapping on the base-emitter and collector characteristics. The accuracy and reliability of any predictions would be questionable.

Besides, what is the benchmark for allowable distortion? The output might appear reasonable but still have appreciable harmonic distortion. Can one easily eyeball 5-10% THD even on a 'pure' sinusoid output?

Why bother?

 

As per t_n_k's suggestion, here is a simple simulation that shows that, regardless of emitter current, you will get massive distortion if you modulate the base-emitter voltage by 120mV p-p.
I made the capacitor 1 Farad, just because I could. Seriously, the reactance of this cap has to be negligible at all frequencies of interest, so I just made it big.
I stepped the emitter current from 100uA to 1mA in 100uA steps, and plotted collector current. The AC base-emitter voltage is 120mV p-p in all cases.
Since the AC output voltage is proportional to collector current, I omitted the collector resistor to prevent saturation from clouding the issue. If you allow saturation, even more distortion will occur.
The conclusion is, you need to attenuate the input voltage.

Trunks14, if you also vary the p-p input voltage, this sim will do what you asked. LTspice has an FFT viewer that will show harmonic distortion.

 

It is obvious that a single class-A transistor needs plenty of negative feedback to have low distortion at high levels. But then its voltage gain is low so many are used to make an opamp that has extremely low distortion.

 

Yes, quite a lot of distortion is inevitable with a simple common-emitter circuit at this level of drive. This should become obvious to you too if you think about what is happening to the transistor. As you can see from your own results, a base drive level of 120mVp-p with the emitter AC grounded results in a large collector current variation. Looking at the page 3 of the data sheet for a 2N3904, it appears that, with Vce constant at 5V, approximately 65mV of change in Vbe will result in the collector current changing by an order of magnitude. http://www.fairchildsemi.com/ds/2N/2N3904.pdf

This implies that the range of collector current variation for 120mV p-p drive would be 10^(120/65) or about 70 times. In practice, the collector current variation in your circuit will be less, because Vce is not constant, and the emitter will not be perfectly grounded. Nevertheless, the current swing is large. Unfortunately, the incremental voltage gain will tend to vary in roughly the same proportion as the collector current, because the mutual conductance of the transistor is approximately proportional to Ic. ( At room temperature, gm≈Ic/0.026).

There should be some reduction of the gain variation because of the changing collector voltage. However, as pointed out by a previous poster, the distortion will actually get worse if the collector saturates. In addition, the input impedance of the transistor will fall as the collector current rises (Zin≈hfe*26/Ic). This may beneficially modify the input waveform if the signal source impedance is comparable to the transistor input impedance.

 

Yes, quite a lot of distortion is inevitable with a simple common-emitter circuit at this level of drive. This should become obvious to you too if you think about what is happening to the transistor. As you can see from your own results, a base drive level of 120mVp-p with the emitter AC grounded results in a large collector current variation. Looking at the page 3 of the data sheet for a 2N3904, it appears that, with Vce constant at 5V, approximately 65mV of change in Vbe will result in the collector current changing by an order of magnitude. http://www.fairchildsemi.com/ds/2N/2N3904.pdf

This implies that the range of collector current variation for 120mV p-p drive would be 10^(120/65) or about 70 times. In practice, the collector current variation in your circuit will be less, because Vce is not constant, and the emitter will not be perfectly grounded. Nevertheless, the current swing is large. Unfortunately, the incremental voltage gain will tend to vary in roughly the same proportion as the collector current, because the mutual conductance of the transistor is approximately proportional to Ic. ( At room temperature, gm≈Ic/0.026).

There should be some reduction of the gain variation because of the changing collector voltage. However, as pointed out by a previous poster, the distortion will actually get worse if the collector saturates. In addition, the input impedance of the transistor will fall as the collector current rises (Zin≈hfe*26/Ic). This may beneficially modify the input waveform if the signal source impedance is comparable to the transistor input impedance.

You can calculate the ΔVbe change required for a 10:1 change in collector current using the Shockley diode equation:

\(I=I_se^{\frac{V_D}{V_T}}\)

For current ratios,

\({\frac{I1}{I2}}=e^{\frac{V_{D1}-V_{D2}}{V_T}}\)

For an order of magnitude change in current,

\(10=e^{\frac{V_{D1}-V_{D2}}{V_T}}\)

\(ln(10)={\frac{V_{D1}-V_{D2}}{V_T}}\)

Let \(\Delta{V_D}={V_{D1}-V_{D2}\)

\(\Delta{V_D}=V_Tln(10)\)

\(\Delta{V_D}=2.3*V_T\)

\(\Delta{V_D}=2.3*0.026\)

\(\Delta{V_D}=60mV\)

Which agrees closely with the value you picked off the datasheet.

 

Hello,

Try this, I can't give you the values because its homework.

But I can walk you thru the calculations.

You don't specify the bandwidth, so just use this freq. to have something to work with.

Fo = 10Khz.
VCC = 12v.
Bmin. = 100
Vin pk = 60mV.
VC = 6v.
VCE = 1v. (data sheet)
IC = 10mA. (data sheet)
Vbe = 0.7v.

1.) IB = (IC / Bmin.) = ?
2.) VE = (VC - VCE) = ?
3.) RE = (VE / IC) = ?
4.) VB = (VE + Vbe) = ?
5.) ID = (10 x IB) = ?
6.) R2 = (VB / ID) = ?
7.) R1 = [(VCC - VB) / ID] = ?

Build / protoype / simulate...stage.

DC bias test:

1.) check voltage at the collector (VC) make sure it is close to calculated value.
2.) check voltage at the base (VB) for close to calculated value.
3.) check emitter voltage (VE).

AC test.

Apply Fo. signal sinewave of 60mV.pk, (120mV p-p), through a large capacitor around 100uF, to the base input.
1.) with simulator or osciloscope, check for any distortion on the input sinewave.
If there is distrtion, lower the input signal voltage until distortion is gone.
2.) then check output signal voltage, for amplitude, and any distortion.

If any distortion, lower input signal until output is clean.

If any distortion occurs on the input signal, then the input impedance is too low.
Changes need to be made with the resistors at the base and emitter.

If any distortion is on the output signal, then the input signal is too large, for this particular bias arangement. Again values would need to be changed.

However The parameters I gave you have been protoyped with a breadboard and shouild show no distortion.

Now you should see that the gain is very little, due to the ratio (RC / RE), this is because, we designed this to have only 1v. drop for VCE. (just for the sake of using the data sheet, value for VCE)
However the large emitter resistor, makes the transistor more stable temperature wise.

Now for CE:

1.) XC = (RE / 10) =?
2.) CE = [(1 / ( 2 * pi. * Fo. * XC)] = ?
3.) Now insert a value close to calculated value into your circuit, and check for BOTH input and output waveform.

If the input waveform is distorted, then CE is making the input impedance too low, so CE needs to be made lower to increase XC.

If input is good and output is distorted, than CE is causing the stage to be overdriven, so gain needs to be lowered by again making CE smaller, to increase XC.
Once you get the proper value for CE, that gives gain with no distortion,
then begin raising the input signal voltage until distortion occurs.

That will allow you to know at what input voltage it can handle.

You can play around with the freq. bandwidth, to see how far both directions on the freq. you can go before the OUTput voltage drops around (0.707 x Vout) = the half power point. which marks out the BW of the stage.

 

In a simulation, input voltage distortion will not exist if the source has zero impedance (it defaults to zero, but can generally be changed, or a resistor can be added external to the source). If the source does have significant impedance, then a common emitter amp such as this one will always cause input distortion, because the input resistance is nonlinear (changes with instantaneous voltage level).
You can't adjust CE as a means of improving input distortion. That will just screw up the frequency response.
Furthermore, for CE, XC<RE/10 is wrong. Emitter bypassing requires that XC<<Re (notice the lower case "e"), which is the dynamic emitter impedance. Re=(26Ω/IE(ma)). For example, when IE=2mA, Re=13Ω. This is generally at least an order of magnitude lower than RE.

 

Hello,

I respect all your authority as you are the professional in this field, as I am only a hobbyist in this, so with all due respect I would like to respond saying,

I realize you need to work with the intrinsic emitter resistance, and ect....

However I am working with this person using first order approximations.

It seems everyone is saying that with this amount of input voltage, that distortion like this person got, is inevitable.

I am trying to show this person, that it is not, that the requirements given, for this project, is not beyond realiziation.

I hardly ever design my circuits with a simulator, unless for what if scenarios, I rather calculate the values, then use a simulator for verification, or to see where my calculations went wrong.

So all my results are done in real time using my function generator, and osciloscope.
The generator Zout~700 ohms.

I built the circuit 3 times, one aproaching from the base voltage, at around 1.8v.
then I redesigned it using a supply of 6v, to show how it can be done with a lower voltage as well.

Then the last time by using the data sheet of 10mA. with 1v for VCE.

The first 2 designs gave a gain of about 20 with and input of 120mVpk (240mVp-p)
just to verify a nondistorted signal at the parameters they were given.
The last design only was able to reliably have a gain of around 10, with nondistortion, using a 70mVpk.
Mainly due to the choice of VCE @ 1v. which changes all the other variables.

Since no bandwidth or Fo. given, I just chose a single freq. to give this person something to work with.

As far as the choice for CE, again I was given this person a first order approximation, of how to choose a bypass capacitor, to get back some AC gain, that has been lost through the swamping of RE.

These designs I gave this person were to get this person thinking in the direction of, how can this be done, rather than," its useless, everyone is saying the input is too loarge, so whats the use of even trying to do this assignment the way it was given".

Not every design can be realized, with parameters given, but a design that CAN be realized, needs to be studied further, to see why it is not being with the methods there using.

When you actually think about it, the only restrictions to this project, is VCC and the input voltage of 120mV p-p.

There are numerous ways of making this realizable, it would be different if a spefic gain or the frequency response were given, THAN there would be more equations and parameters involved, but it looks like they can choose there own freq., without a bandwidth, so they can design a large bandwidth, or a narrow BW, large gain or small gain.

This is a project for them to be very creative in there learning of a simple CE amp stage...

 

Well, he did say that CE must be greater than CI or CO, but if those are the only restrictions, have a field day. No sweat designing a circuit that works at one frequency. Suppose he builds it, and the prof says, "Ok, looks good a 10kHz. Let's see how it works at 100Hz, 1kHz, and 100kHz". He'll probably not get a good grade if others have designed working, relatively broadband amplifiers.
You did mention lowering the input level. I personally think that is the only practical alternative.
I suspect that, if the prof did not mention bandwidth, it was intentional, not so the student could have an easy job at a single frequency, but to stretch their minds and see if they take bandwidth into consideration.

 

I suspect that, if the prof did not mention bandwidth, it was intentional, not so the student could have an easy job at a single frequency, but to stretch their minds and see if they take bandwidth into consideration.

Well, yeh,
that's a good point too.

I guess it all depends on what all, they have learned thus far, to be able to put into practice, in dsigning a single stage amp.

I think if the OP were to post his original values that got him his results, then we could have an idea of what he's doing or not doing to get better results.

 

50 years ago single transistors were used and nobody "heard" the distortion and nobody saw it on a 'scope. For the last 20 years opamps were used with almost no distortion (0.00008%).

 

The objective of the lab is to see the transistor's frequency response. We have to vary the frequency and see that there are two cutoff frequencies, fL and fH, which define the bandwidth. The hard restrictions are Vcc = 12V, and Vin = 120 mV p-p (this is not imposed by the professor but rather most of the function generators we have are in this range, although I later found out that there are some that will let you get ~40 mV p-p, which I may have to use).

If I learned anything from this it's that you have to pay close attention to the restrictions imposed by a model, in this case the small signal model. I just wish the book I was using (Boylestad) had gone into more detail as to how small is small enough.

@hobbyist: I appreciate your help and I realize that had I stated from the beginning that there should be a bandwidth in which the transistor would work (although no specific bandwidth was imposed to us), maybe you would've told me straight out that it wasn't possible with that large of an input signal. At this point I don't think you could come up with a design that shows no distortion in the medium frecuencies (i.e. the capacitors are seen as short circuits by the AC signal) with a ~120 mV p-p input signal. Feel free to prove me wrong if it can be realized.

@Audioguru: I bet 50 years ago they weren't forced to use this configuration and choice of input signal =P?