Either you misunderstood your teacher, or the teacher is wrong. With 5 variables, a fully populated truth table would have 32 rows:
View attachment 148684
It's the don't cares in the rows for invalid counts that lets you simplify the logic.

Other than reversing the polarity of the count direction variable, our tables would be the same.

After doing what you tell me, got this.

j3= A'Q2Q1Q0 + AQ2'Q1'Q0'
K3= A'Q0 + AQ0'
J2= A'Q0 + AQ0'
K2= A'Q0 + AQ0'
J1= A'Q0 + AQ0'
K1= A'Q0 + AQ0'

 

I agree with J3 and K1. You got the correct answer for K3, but the groupings you made don't give that result.

Since you aren't color coding the groupings, you need to use arrows to associate disjointed groupings.

 

I agree with J3 and K1. You got the correct answer for K3, but the groupings you made don't give that result.

Since you aren't color coding the groupings, you need to use arrows to associate disjointed groupings.

Here are my ec.
J3= A'Q2Q1Q0 + AQ2'Q1'Q0'
K3= A'Q0 + AQ0'
J2= AQ3Q1'Q0' + Q'Q1Q0
K2= AQ1'Q0'+ A'Q1Q0
J1= A'Q3'Q0 + AQ2Q0' + AQ3Q0'
K1= A'Q0 + AQ0'

Here I attach my design in multisim, It goes correctly then gets crazy

 

J2= AQ3Q1'Q0' + Q'Q1Q0

Check this equation. I assume Q' is supposed to be A'.

Can you post the J2 Kmap with the groupings clearly marked?

 

Check this equation. I assume Q' is supposed to be A'.

Can you post the J2 Kmap with the groupings clearly marked?

Oh yeah, sorry It´s :
J2= A'Q1Q0+ AQ3Q0'

 

It´s :
J2= A'Q1Q0+ AQ3Q0'

Looks like you've got it sorted out.

 

Looks like you've got it sorted out.

But, if you take a look at my schematic, it doesn't count well, any idea ?

 

But, if you take a look at my schematic, it doesn't count well, any idea ?

It must be a wiring error.

Can you post a screen shot of your schematic? I don't open .rar files and my free version of MultiSIM Blue has few usable components.

 

It must be a wiring error.

Can you post a screen shot of your schematic? I don't open .rar files and my free version of MultiSIM Blue has few usable components.

Here it is.

 

Here it is.

Your lack of style makes troubleshooting more difficult than it should be. The format I showed you makes it easy to troubleshoot. I only use the style you're trying to use after the logic has been verified; and do that only if it's required.

Using color coded nets without a legend is pointless.

What is the count sequence you're getting?

 

What

I get 9,8,7,6,5 then it goes tu 9 again and then it gets trubleshoot. Up count goes from 0 then 7 and 9

 

Up count goes from 0 then 7 and 9

Lets start by debugging the count up problem.

With the counter at 0, look at the inputs the B (with A being least significant and D most significant) and C flip flops. They should be set to something that will cause them to do nothing, or reset. If that isn't the case, look at the inputs that are wrong and determine why.

If Multisim doesn't support single stepping, replace the clock with a switch.

 

Here it is.

When I used Multisim, I found that things can look connected, but not be connected. I got into the habit of grabbing components on nets I was tracing and moving them around to see if the wires followed.

It's tendency to create scenic routes was also annoying. You can use the shift key to force the route to be cleaner.

Instead of posting screen shots with extraneous information, you can print to PDF and post only the relevant portion. Unless the color coding of nets is meaningful, print in black and white.

What version of Multisim are you using? I tried to open the last file you posted and it was incompatible with my version.

 

When I used Multisim, I found that things can look connected, but not be connected. I got into the habit of grabbing components on nets I was tracing and moving them around to see if the wires followed.

It's tendency to create scenic routes was also annoying. You can use the shift key to force the route to be cleaner.

Instead of posting screen shots with extraneous information, you can print to PDF and post only the relevant portion. Unless the color coding of nets is meaningful, print in black and white.

What version of Multisim are you using? I tried to open the last file you posted and it was incompatible with my version.

I am using NI Multisim 14.0 Power Pro Edition

 

Cropped, edited schematic:

I removed the 7 segment display since it was black in the PDF.

Since the up count sequence is 0,7,9; get the counter to 0 and look at the inputs to the flip flops to see which are causing it to not increment to 2 1.
EDIT: Corrected count.

BTW, when I connected the counter making the mistakes I noticed, I don't get the count sequences you mentioned.

 

Cropped, edited schematic:
View attachment 148892
I removed the 7 segment display since it was black in the PDF.

Since the up count sequence is 0,7,9; get the counter to 0 and look at the inputs to the flip flops to see which are causing it to not increment to 2.

BTW, when I connected the counter making the mistakes I noticed, I don't get the count sequences you mentioned.

Problem solved.

I was wiring some ANDS in they wrong way, didn´t notice cause I was a little tired.

Thanx for your help, here It´s the schematic working from 0-9 and 9-0.

 

Problem solved.

Glad you found the problem.

You should do yourself a favor and develop some style. Most prefer for the logic to flow from left to right and top to bottom. You should avoid unnecessary wire jogs and backtracks.

Multisim has gates with more than 2 inputs; use them. You can also move the logic gate text out of the way so you don't have to route wires over text.

I was wiring some ANDS in they wrong way, didn´t notice cause I was a little tired.

From what I traced, it was more than just wiring some ANDs incorrectly. A couple gates were using Q1' when they should have used Q1, J1 used Q2 in one minterm when it should have been Q3, and the K2 expression was really messed up.

These problems would have been more apparent in a neater schematic.

In this schematic, I moved the text for the gates into the symbols to get it out of the way:

 

You should do yourself a favor and develop some style. Most prefer for the logic to flow from left to right and top to bottom. You should avoid unnecessary wire jogs and backtracks.

Multisim has gates with more than 2 inputs; use them. You can also move the logic gate text out of the way so you don't have to route wires over text.

I see, thanx for the info I will do it as you suggested. I am kinda new to this so I´m still learning kinda by myself.
I used gates with 2 inputs cause I just had gates with 2 inputs and wanted to move from multisim to a proto.

Thanx for the information, will see next time.

 

I am kinda new to this so I´m still learning kinda by myself.

Your teacher should be showing you how to draw schematics neatly and make deductions for sloppy work.

You can also learn by looking at schematics drawn by others, particularly professionals. This is from TI:

This schematic could be improved slightly, but I forgive the creator because they drew by hand back in those days using templates, straight edges, and ink pens.

You can even learn from poorly drawn schematics; what not to do...